• Pipelined on 5 stages (Fetch Decode Execute0 Execute1 WriteBack)
  • Multiple branch prediction modes : (disable, static or dynamic)
  • Data path parameterizable between fully bypassed to fully interlocked


  • One cycle multiplication
  • 34 cycle division
  • Iterative shifter (N shift -> N cycles)
  • Single cycle shifter
  • Interruption controller
  • Debugging module (with JTAG bridge, openOCD port and GDB)
  • Instruction cache with wrapped burst memory interface, one way
  • Data cache with instructions to evict/flush the whole cache or a given address, one way

Performance/Area (on cyclone II)

  • small core -> 846 LE, 0.6 DMIPS/Mhz
  • debug module (without JTAG) -> 240 LE
  • JTAG Avalon master -> 238 LE
  • big core with MUL/DIV/Full shifter/I$/Interrupt/Debug -> 2200 LE, 1.15 DMIPS/Mhz, at least 100 Mhz (with default synthesis option)

Base FPGA project

You can find a DE1-SOC project which integrate two instance of the CPU with MUL/DIV/Full shifter/I$/Interrupt/Debug there :


CPU/JTAG/VGA IP are pre-generated. Quartus Prime : 15.1.

How to generate the CPU VHDL

There is an example of a top level which generate an Altera QSys component that contain the CPU with Avalon interfaces and some timing buffer :


If you want to generate it, the easiest way is to get the https://github.com/SpinalHDL/SpinalTemplateSbt and call QSysAvalonCore.main(null) from your main function.

How to debug

You can find the openOCD fork there :


An example target configuration file could be find there :


Then you can use the RISCV GDB.


  • Documentation
  • Optimise instruction/data caches FMax by moving line hit condition forward into combinatorial paths.

Contact spinalhdl@gmail.com for more information