R
MWR
RASn
SdramInterface
READ
Axi4ToBRAMPhase I2cSlaveCmdMode SdramCtrlBackendTask
REFERENCECLK
SB_PLL40_CORE
REFRESH
SdramCtrlBackendTask
RESERVED
burst Response
RESET
JtagState
RESETB
SB_PLL40_CORE SB_PLL40_PAD
RESPONSE
Phase Axi4ToApb3BridgePhase Axi4ToBRAMPhase
RESTART
I2cSlaveCmdMode
RISING
core
RS
OP0 OP1
RTY
Wishbone
RUN
SdramCtrlFrontendState
Ram_1w_1ra
core
Ram_1w_1rs
core
Ram_1wors
core
Ram_1wrs
core
Ram_2c_1w_1rs
core
Ram_2wrs
core
RangePimper
core
RangedAssignmentFixed
internals
RangedAssignmentFloating
internals
ReadMapping
SpiXdrMasterCtrl
ReadRetLinked
lib
ReadUnderWritePolicy
core
ReadableOpenDrain
io
RecFloating
math
RecFloating128
math
RecFloating16
math
RecFloating32
math
RecFloating64
math
Ref
core
RefOwnerType
OwnableRef
Reg
core
RegFileReadKind
impl
RegFlow
lib
RegInit
core
RegNext
core
RegNextWhen
core
Report
bench
Request
PlicTarget
ResetArea
core
ResetCtrl
lib
ResetEmitterEmitter
altera
ResetEmitterTag
altera
ResetKind
core
ResetTag
core
Resize
internals
ResizeBits
internals
ResizeSInt
internals
ResizeUInt
internals
Response
AvalonMM
Reverse
lib
Rgb
graphic
RgbConfig
graphic
RiscvAhbLite3
build
RiscvAvalon
build
RiscvAxi4
build
RiscvCore
impl
RiscvCoreConfig
impl
Rise
Formal
Rsp
SpiXdrMasterCtrl
Rtl
bench
r
Axi4 Axi4ReadOnly Axi4Shared AxiLite4 AxiLite4ReadOnly Rgb
rUserWidth
Axi4Config
rWidth
RgbConfig
ram
StreamFifoCC StreamFifoLowLatency AhbLite3OnChipRam AhbLite3OnChipRom Axi4SharedOnChipRam
ramBlock
core
randBoot
Data Mem
randomAddressInRange
AddressRange
randomAdressInRange
WishboneTransaction
randomBoot
core
randomize
SimBaseTypePimper SimBitsPimper SimBoolPimper SimDataPimper SimEnumPimper SimSIntPimper SimUIntPimper
randomizeAddress
WishboneTransaction
randomizeData
WishboneTransaction
randomizeTGA
WishboneTransaction
randomizeTGC
WishboneTransaction
randomizeTGD
WishboneTransaction
range
BitVector Vec
rate
XdrOutput XdrPin
raw
XFix
rawFactory
SFix UFix XFix
rddata
BRAM
read
Vec TraversableOncePimped Apb3Driver AvalonMM BusSlaveFactory JtagTapAccess SpiMasterCtrlCmdData Cmd XdrPin UartCtrlIo ReadableOpenDrain TriState TriStateArray
readAddress
AhbLite3SlaveFactory Apb3SlaveFactory AxiLite4SlaveFactory AvalonMMSlaveFactory BRAMSlaveFactory BusSlaveFactory BusSlaveFactoryAddressWrapper AsyncMemoryBusFactory PipelinedMemoryBusSlaveFactory WishboneSlaveFactory
readAndClearOnSet
BusSlaveFactory
readAndSetOnSet
BusSlaveFactory
readAndWrite
BusSlaveFactory
readAndWriteMultiWord
BusSlaveFactory
readAsync
Mem
readAsyncImpl
Mem
readAtCmd
AvalonMMSlaveFactory PipelinedMemoryBusSlaveFactory
readAtRsp
AvalonMMSlaveFactory PipelinedMemoryBusSlaveFactory
readClockEnableWire
ClockDomain
readClockWire
ClockDomain
readCmd
Axi4 Axi4ReadOnly AxiLite4 AxiLite4ReadOnly
readData
Axi4SharedToBram AvalonMM AsyncMemoryBus
readDataStage
AxiLite4SlaveFactory
readDataValid
AvalonMM
readDecodings
Axi4SharedDecoder
readEnable
MemReadSync
readFirst
core
readHalt
AhbLite3SlaveFactory Apb3SlaveFactory AxiLite4SlaveFactory AvalonMMSlaveFactory BRAMSlaveFactory BusSlaveFactory BusSlaveFactoryAddressWrapper AsyncMemoryBusFactory PipelinedMemoryBusSlaveFactory WishboneSlaveFactory
readHaltRequest
AxiLite4SlaveFactory
readHexFile
HexTools
readIdPathRange
Axi4SharedArbiter
readInputConfig
Axi4SharedArbiter
readInputsCount
Axi4SharedArbiter
readLatency
AvalonMMConfig
readMapping
Mod
readMultiWord
BusSlaveFactory
readOccur
AxiLite4SlaveFactory
readOnlyBridger
Axi4CrossbarFactory
readPrimitive
BusSlaveFactory BusSlaveFactoryAddressWrapper BusSlaveFactoryDelayed
readRange
Axi4SharedArbiter Axi4SharedDecoder
readResetWire
ClockDomain
readRsp
Axi4 Axi4ReadOnly Axi4Shared AxiLite4 AxiLite4ReadOnly AxiLite4SlaveFactory
readRspIndex
Axi4ReadOnlyArbiter Axi4ReadOnlyDecoder Axi4SharedArbiter Axi4SharedDecoder
readRspInputs
Axi4SharedArbiter
readRspSels
Axi4ReadOnlyArbiter Axi4SharedArbiter
readSoftResetWire
ClockDomain
readStreamNonBlocking
BusSlaveFactory
readSync
Mem
readSyncCC
Mem
readSyncImpl
Mem
readSyncMemWordAligned
BusSlaveFactory
readSyncMixedWidth
Mem
readSyncPort
MemPimped
readType
ReadRetLinked
readUnderWrite
MemReadAsync MemReadSync
readUnderWriteString
ReadUnderWritePolicy dontCare readFirst writeFirst
readWaitTime
AvalonMMConfig
readWriteSync
Mem MemTopology
readWriteSyncImpl
Mem
readWriteSyncMixedWidth
Mem
readedData
AhbLite3ToApb3Bridge Axi4SharedToApb3Bridge
readedOutputWrapEnable
ComponentEmitter ComponentEmitterVhdl
readsAsync
MemTopology
readsSync
MemTopology
ready
Stream AsyncMemoryBus
reduceBalancedTree
TraversableOnceAnyPimped TraversableOncePimped
ref
ScoreboardInOrder
refImpl
ComponentEmitterVerilog ComponentEmitterVhdl
refOwner
OwnableRef
referenceSetAdd
ComponentEmitterVerilog ComponentEmitterVhdl
referenceSetPause
ComponentEmitterVerilog ComponentEmitterVhdl
referenceSetResume
ComponentEmitterVerilog ComponentEmitterVhdl
referenceSetSorted
ComponentEmitterVerilog ComponentEmitterVhdl
referenceSetStart
ComponentEmitterVerilog ComponentEmitterVhdl
referenceSetStop
ComponentEmitterVerilog ComponentEmitterVhdl
referencesOverrides
ComponentEmitter
reflect
Misc
reflectExclusion
Misc
reflectNames
Area
reflectiveCalls
core
refresh
SdramCtrl
reg
EventEmitter
regFile
RiscvCore
regFileAddress
CoreExecute1Output
regFileReadyKind
RiscvCoreConfig
region
Axi4Ax Axi4AxUnburstified
registerFile
core
release
Phase
remainder
MixedDividerRsp SignedDividerRsp UnsignedDivider UnsignedDividerRsp
remainderMinusDenominator
UnsignedDivider
remainderShifted
UnsignedDivider
remaining
Axi4ReadOnlyErrorSlave Axi4SharedErrorSlave
remainingZero
Axi4ReadOnlyErrorSlave Axi4SharedErrorSlave
remapAddress
AhbLite3
remapDrivingExpressions
AssignmentStatement BitAssignmentFixed BitAssignmentFloating ExpressionContainer RangedAssignmentFixed RangedAssignmentFloating
remapElementsExpressions
SwitchStatement
remapExpressions
MemReadAsync MemReadSync MemReadWrite MemWrite AnalogDriver AssertStatement AssignmentStatement BinaryMultiplexer BinaryOperator BitAssignmentFixed BitAssignmentFloating BitVectorBitAccessFixed BitVectorBitAccessFloating BitVectorRangedAccessFixed BitVectorRangedAccessFloating Cast ConstantOperator DeclarationStatement ExpressionContainer Literal Multiplexer InitState RangedAssignmentFixed RangedAssignmentFloating Resize SwitchStatement SwitchStatementKeyBool UnaryOperator WhenStatement
remoteCmdWidth
SystemDebuggerConfig
remove
AssignedBits
removeAssignments
BaseType Data
removeOffset
AddressMapping DefaultMapping MaskMapping SingleMapping SizeMapping
removeStatement
BaseType Statement StatementDoubleLinkedContainerElement
removeStatementFromScope
Statement
removeTag
SpinalTagReady
removeTags
SpinalTagReady
replaceStdLogicByStdULogic
BlackBox
report
core
requestIndex
AhbLite3Decoder
requests
WishboneArbiter PlicTarget
resendTimeout
SerialLinkTx
reservedKeyWords
PhaseContext
reset
ClockDomain GlobalData SafeStack
resetActiveLevel
ClockDomainConfig
resetCtrl
Pinsec
resetCtrlClockDomain
Pinsec
resetKind
ClockDomainConfig
resetOut
DebugExtensionIo
resetSim
SimClockDomainPimper
resize
BitVector Bits SInt UInt InputNormalize
resizeFactory
Bits Add And Or Sub Xor And Or Xor Add And Or Sub Xor Add And Or Sub Xor
resizeFunction
ComponentEmitterVhdl
resizeLeft
Bits
resized
Data
resizedOrUnfixedLit
InputNormalize
resolution
SFix UFix XFix
resp
Axi4 Axi4B Axi4R AxiLite4 AxiLite4B AxiLite4R
response
AvalonMM
result
ComponentEmitterVerilog ComponentEmitterVhdl CoreExecute0Output CoreExecute1Output TopLevel
retain
Phase
retainFor
Phase
retainer
Phase
rework
Component
rfen
InstructionCtrl
rgbConfig
Axi4VgaCtrlGenerics Vga VgaCtrl
right
BinaryOperator
riscv
cpu
rise
Bool BoolEdges Formal
risingEdge
SimClockDomainPimper
risingOccupancy
StreamFifoLowLatency
rootScopeStatement
BaseType AssignmentStatement Statement
rotateLeft
BitVector Bits SInt UInt
rotateRight
BitVector Bits SInt UInt
roundRobin
OHMasking Arbitration StreamArbiterFactory
roundUp
core
routeBuffer
Axi4SharedArbiter Axi4WriteOnlyArbiter
routeBufferSize
Axi4SharedArbiter Axi4WriteOnlyArbiter
routeDataInput
Axi4SharedArbiter Axi4WriteOnlyArbiter
row
SdramCtrlBank
rowColumn
SdramCtrlBackendCmd
rowWidth
SdramLayout
rsp
MemReadPort AvalonReadDma PipelinedMemoryBus I2cSlaveBus XipBus CoreDataBus CoreInstructionBus DataCacheCpuBus DataCacheMemBus InstructionCacheCpuBus InstructionCacheFlushBus InstructionCacheMemBus DebugExtensionBus Ctrl Mem VideoDmaMem SdramCtrlBus SystemDebuggerMemBus SystemDebuggerRemoteBus
rspArea
Block VideoDma
rspBit
SpiSlaveCtrl
rspBitSampled
SpiSlaveCtrl
rspFifoDepth
SpiMasterCtrlMemoryMappedConfig MemoryMappingParameters
rspPipe
PipelinedMemoryBus
rspRouteQueue
PipelinedMemoryBusArbiter
rtl
SpinalVerilatorBackendConfig
rtlHeader
SpinalConfig
rtlSourcesPaths
SpinalReport
run
Axi4VgaCtrl
rwn
AsyncMemoryBus
rx
SpiSlaveCtrlIo UartCtrl
rxFifoDepth
SpiSlaveCtrlMemoryMappedConfig UartCtrlMemoryMappedConfig
rxPtr
SerialLinkRx SerialLinkRxToTx
rxSamplePerBit
UartCtrlGenerics
rxd
Uart