==========
Simulation
==========

As always, you can use your standard simulation tools to simulate the VHDL/Verilog generated by SpinalHDL.
However, since SpinalHDL 1.0.0, the language integrates an API to write testbenches and test your hardware
directly in Scala. This API provides the capabilities to read and write the DUT signals, fork and join
simulation processes, sleep and wait until a given condition is reached. Therefore, using SpinalHDL's
simulation API, it is easy to integrate testbenches with the most common Scala unit-test frameworks.

To be able to simulate user-defined components, SpinalHDL uses external HDL simulators as backend. Currently, four simulators are supported:

- `Verilator <https://www.veripool.org/verilator/>`_
- `GHDL <http://ghdl.free.fr/>`_
- `Icarus Verilog <https://steveicarus.github.io/iverilog/>`_
- `VCS <https://www.synopsys.com/verification/simulation/vcs.html>`_ **(experimental, since SpinalHDL 1.7.0)**
- `XSim <https://www.google.com/search?q=site%3Axilinx.com+xsim>`_ **(experimental, since SpinalHDL 1.7.0)**

With external HDL simulators it is possible to directly test the generated HDL sources without increasing the SpinalHDL codebase complexity.

.. toctree::
   :hidden:
   
   install/index
   bootstraps
   signal
   clock
   threadFull
   threadLess
   sensitive
   simulator_specifics
   engine
   examples/index