trait TraceBackend extends AnyRef
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Abstract Value Members
- abstract def addRegion(hartId: Int, kind: Int, base: Long, size: Long): Unit
- abstract def close(): Unit
- abstract def commit(hartId: Int, pc: Long): Unit
- abstract def flush(): Unit
- abstract def ioAccess(hartId: Int, access: TraceIo): Unit
- abstract def loadBin(offset: Long, path: File): Unit
- abstract def loadBytes(offset: Long, bytes: Array[Byte]): Unit
- abstract def loadCommit(hartId: Int, id: Long): Unit
- abstract def loadElf(offset: Long, path: File): Unit
- abstract def loadExecute(hartId: Int, id: Long, addr: Long, len: Long, data: Long): Unit
- abstract def loadFlush(hartId: Int): Unit
- abstract def newCpu(hartId: Int, isa: String, priv: String, physWidth: Int, pmpNum: Int, memoryViewId: Int): Unit
- abstract def newCpuMemoryView(viewId: Int, readIds: Long, writeIds: Long): Unit
- abstract def readRf(hardId: Int, rfKind: Int, address: Int, data: Long): Unit
- abstract def setInterrupt(hartId: Int, intId: Int, value: Boolean): Unit
- abstract def setPc(hartId: Int, pc: Long): Unit
- abstract def storeBroadcast(hartId: Int, id: Long): Unit
- abstract def storeCommit(hartId: Int, id: Long): Unit
- abstract def storeConditional(hartId: Int, failure: Boolean): Unit
- abstract def storeExecute(hartId: Int, id: Long, addr: Long, len: Long, data: Long): Unit
- abstract def time(value: Long): Unit
- abstract def trap(hartId: Int, interrupt: Boolean, code: Int): Unit
- abstract def writeRf(hardId: Int, rfKind: Int, address: Int, data: Long): Unit
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##(): Int
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==(arg0: Any): Boolean
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- def addRegion(hartId: Int, kind: Int, mapping: AddressMapping): Unit
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final
def
notifyAll(): Unit
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- @native() @IntrinsicCandidate()
- def spinalSimFlusher(period: Long): TraceBackend.this.type
- def spinalSimPeriod(period: Long): Unit
- def spinalSimTime(period: Long): Unit
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finalize(): Unit
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