case class DfiConfig(chipSelectNumber: Int, dataSlice: Int, signalConfig: DfiSignalConfig, timeConfig: DfiTimeConfig, sdram: SdramConfig) extends Product with Serializable
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Instance Constructors
- new DfiConfig(chipSelectNumber: Int, dataSlice: Int, signalConfig: DfiSignalConfig, timeConfig: DfiTimeConfig, sdram: SdramConfig)
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final
def
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def
##(): Int
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def
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- val addressWidth: Int
- val alertWidth: Int
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- val bankGroupWidth: Int
- val bankWidth: Int
- val beatCount: Int
- val beatWidth: Int
- val burstWidth: Int
- val bytePerBeat: Int
- val bytePerBurst: Int
- val bytePerDq: Int
- val caTrainingMCIFWidth: Int
- val caTrainingPhyIFWidth: Int
- val caTrainingResponseWidth: Int
- val chipIdWidth: Int
- val chipSelectNumber: Int
- val chipSelectWidth: Int
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def
clone(): AnyRef
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- val controlWidth: Int
- val dataEnableWidth: Int
- val dataRate: Int
- val dataSlice: Int
- val dataWidth: Int
- val dbiWidth: Int
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final
def
eq(arg0: AnyRef): Boolean
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- val errorNumber: Int
- val frequencyRatio: Int
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- val levelingPhyIFWidth: Int
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notify(): Unit
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final
def
notifyAll(): Unit
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- val phyIoWidth: Int
- val rankWidth: Int
- val readDataValidWidth: Int
- val readLevelingMCIFWidth: Int
- val readLevelingPhyIFWidth: Int
- val readLevelingResponseWidth: Int
- val readTrainingPhyIFWidth: Int
- val sdram: SdramConfig
- val signalConfig: DfiSignalConfig
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final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
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- val taskAddressWidth: Int
- val timeConfig: DfiTimeConfig
- val transferPerBurst: Int
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(): Unit
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- val writeLevelingMCIFWidth: Int
- val writeLevelingPhyIFWidth: Int
- val writeLevelingResponseWidth: Int
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