Packages

package lib

Linear Supertypes
AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. lib
  2. AnyRef
  3. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Type Members

  1. class AnalysisUtils extends AnyRef
  2. class AnyPimped[T] extends AnyRef
  3. implicit class BigIntRicher extends LiteralRicher
  4. implicit class BinIntsRicher extends AnyRef
  5. implicit class BinaryBuilder extends AnyRef
  6. implicit class BinaryBuilder2 extends AnyRef
  7. class BitAggregator extends AnyRef
  8. class BoolPimped extends AnyRef
  9. sealed trait BoundaryPolicy extends AnyRef
  10. abstract class BoundedCounter[T <: BitVector] extends ImplicitArea[T] with CounterLike[T] with CounterAddressable[T]
  11. class BufferCC[T <: Data] extends Component
  12. class BufferCCBlackBox extends BlackBox
  13. implicit class ByteRicher extends LiteralRicher
  14. implicit class BytesRicher extends AnyRef
  15. class ClockDomainPimped extends AnyRef
  16. class Counter extends BoundedCounter[UInt]
  17. trait CounterAddressable[T <: BitVector] extends ImplicitArea[T] with CounterLike[T]
  18. sealed trait CounterDirection extends AnyRef
  19. trait CounterLike[T <: BitVector] extends ImplicitArea[T]
  20. class CounterUpDown extends Counter
  21. trait DataCarrier[T <: Data] extends AnyRef
  22. class DataCarrierFragmentBitsPimped extends AnyRef
  23. class DataCarrierFragmentPimped[T <: Data] extends AnyRef
  24. case class DataOr[T <: Data](dataType: HardType[T]) extends Area with Product with Serializable
  25. type Event = Stream[NoData]
  26. case class EventEmitter(on: Event) extends Product with Serializable
  27. class EventFactory extends MSFactory
  28. class Flow[T <: Data] extends Bundle with IMasterSlave with DataCarrier[T]
  29. class FlowArbiterBuilder[T <: Data] extends AnyRef
  30. class FlowBitsPimped extends AnyRef
  31. class FlowCCUnsafeByToggle[T <: Data] extends Component

    CDC for a Flow, NOT SAFE for general use

    CDC for a Flow, NOT SAFE for general use

    See also

    UnsafeFlowCCByToggle.apply

  32. class FlowCmdRsp[T <: Data, T2 <: Data] extends Bundle with IMasterSlave
  33. class FlowFactory extends MSFactory
  34. class FlowFragmentBitsRouter extends AnyRef
  35. class FlowFragmentFactory extends MSFactory
  36. class FlowFragmentPimped[T <: Data] extends AnyRef
  37. class Fragment[T <: Data] extends Bundle
  38. class FragmentFactory extends AnyRef
  39. class GrayCounter extends BoundedCounter[UInt]
  40. class GrowableAnyPimped[T] extends AnyRef
  41. class HistoryModifyable[T <: Data] extends Component
  42. trait IMasterSlave extends AnyRef

    An interface that a Bundle can implement if it obeys to a master/slave topology.

    An interface that a Bundle can implement if it obeys to a master/slave topology.

    See also

    Bundle documentation

  43. implicit class IntRicher extends LiteralRicher
  44. class JohnsonCounter extends ImplicitArea[Bits] with CounterLike[Bits]
  45. trait LiteralRicher extends AnyRef
  46. implicit class LongRicher extends LiteralRicher
  47. sealed trait MS extends AnyRef

    Declare a port as master or slave

    Declare a port as master or slave

    There are 4 available syntaxes, which are all equivalent:

    val braces = master(Flow(Bool))

val short = master Flow (Bool)

val spaceful = master port Flow(Bool)

val variadic = Flow(Bool)
master(variadic)

    The "braces" syntax is short and generic, but it uses braces.

    The "short" syntax is short, but it is formatted with a space between the type and its parameters, and it can be used only with:

    • Flow
    • Stream

    The "spaceful" syntax is generic and beautiful, but more verbose.

    The "variadic" syntax can be used with any number of interfaces, but can be used only if the interfaces are already declared.

    See also

    master slave

  48. trait MSFactory extends AnyRef

    Something which can create master/slave interfaces

  49. class MemPimped[T <: Data] extends AnyRef
  50. case class MemReadPort[T <: Data](dataType: T, addressWidth: Int) extends Bundle with IMasterSlave with Product with Serializable
  51. case class MemReadPortAsync[T <: Data](dataType: T, addressWidth: Int) extends Bundle with IMasterSlave with Product with Serializable
  52. case class MemReadStreamFlowPort[T <: Data](dataType: T, addressWidth: Int) extends Bundle with IMasterSlave with Product with Serializable
  53. case class MemReadWritePort[T <: Data](dataType: T, addressWidth: Int, maskWidth: Int = -1) extends Bundle with IMasterSlave with Product with Serializable

    Master/slave interface to a

    Master/slave interface to a

    See also

    Mem.readWriteSyncPort()

  54. case class MemWriteCmd[T <: Data](dataType: HardType[T], addressWidth: Int, maskWidth: Int = -1) extends Bundle with Product with Serializable
  55. case class MemWriteCmdWithMask[T <: Data](mem: Mem[T], maskWidth: Int) extends Bundle with Product with Serializable
  56. class MuxOHImpl extends AnyRef
  57. class NoData extends Bundle
  58. class OneHotCounter extends BoundedCounter[Bits]
  59. class PackedBundle extends Bundle

    Similar to Bundle but with bit packing capabilities.

    Similar to Bundle but with bit packing capabilities. Use pack implicit functions to assign fields to bit locations - pack(Range, [Endianness]) - Packs the data into Range aligning to bit Endianness if too wide - packFrom(Position) - Packs the data starting (LSB) at Position. Uses full data length - packTo(Position) - Packs the data ending (MSB) at Position. Uses full data length

    Providing no location tag will place the next data value immediately after the last.

    Example: 

    1. val regWord = new PackedBundle {
  val init = Bool().packFrom(0) // Bit 0
  val stop = Bool() // Bit 1
  val result = Bits(16 bit).packTo(31) // Bits 16 to 31
}
  60. class PackedWordBundle extends PackedBundle

    An enhanced form of PackedBundle with Word-centric packing.

    An enhanced form of PackedBundle with Word-centric packing. Offers all the same implicit packing assignment functions, but applies packing to an assigned word. - inWord(WordIndex) - Indicates which word to pack into. Must be used after a pack assignment. If no pack range was given then the entire data length will be assumed. Ranges that exceed the word will wrap into subsequent words.

    Like PackedBundle, providing no pack or word assignments will place data immediately after the last.

    Example: 

    1. val wordPacked = PackedWordBundle(8 bits) {
  val aNumber = UInt(8 bits).word(0) // Bits 7 downto 0
  val bNumber = UInt(8 bits).pack(0 to 7).word(1) // Bits 8 to 15
  val large   = Bits(18 bits).word(2) // Bits 33 downto 16
  val flag    = Bool() // Bit 34
  61. class PhaseBufferCCBB extends PhaseNetlist
  62. class PulseCCByToggle extends Component
  63. case class ReadRetLinked[T <: Data, T2 <: Data](readType: HardType[T], linkedType: HardType[T2]) extends Bundle with Product with Serializable
  64. class ResetAggregator extends Area
  65. case class ResetAggregatorSource(pin: Bool, sync: Boolean, pol: Polarity) extends Product with Serializable
  66. class ResetCtrlFiber extends Area
  67. class ResetHolder extends Area
  68. class SamplerCC[T <: Data] extends BlackBox
  69. type ScalaStream[T] = scala.collection.immutable.Stream[T]
  70. sealed trait SlicesOrder extends AnyRef

    Enumeration to present order of slices.

  71. class Stream[T <: Data] extends Bundle with IMasterSlave with DataCarrier[T]

    A simple interface with master payload valid, slave ready handshake.

    A simple interface with master payload valid, slave ready handshake.

    When manually reading/driving the signals of a Stream keep in mind that:

    • After being asserted, valid may only be deasserted once the current payload was acknowledged. This means valid can only toggle to 0 the cycle after a the slave did a read by asserting ready.
    • In contrast to that ready may change at any time.
    • A transfer is only done on cycles where both valid and ready are asserted.
    • valid of a Stream must not depend on ready in a combinatorial way and any path between the two must be registered.

    It is recommended that valid does not depend on ready at all.

    See also

    Stream documentation

  72. class StreamAccessibleFifo[T <: Data] extends Component
  73. class StreamArbiter[T <: Data] extends Component

    Arbitrate from several Stream to one with various algorithms.

    Arbitrate from several Stream to one with various algorithms.

    A StreamArbiter is like a StreamMux, but with built-in complex selection logic that can arbitrate input streams based on a schedule or handle fragmented streams.

    Use a StreamArbiterFactory to create instances of this class.

    See also

    Stream documentation

  74. class StreamArbiterFactory extends AnyRef

    Build a StreamArbiter from a list of Stream.

    Build a StreamArbiter from a list of Stream.

    example:

    val streamA, streamB, streamC = Stream(Bits(8 bits))
val arbiteredABC = StreamArbiterFactory.roundRobin.onArgs(streamA, streamB, streamC)
val streamD, streamE, streamF = Stream(Bits(8 bits))
val arbiteredDEF = StreamArbiterFactory.lowerFirst.noLock.onArgs(streamD, streamE, streamF)
    See also

    Stream documentation

  75. class StreamBitsPimped extends AnyRef
  76. class StreamBundlePimped[T <: Bundle] extends AnyRef
  77. class StreamCCByToggle[T <: Data] extends Component
  78. class StreamDelay[T <: Data] extends Component
  79. class StreamDemux[T <: Data] extends Component
  80. class StreamFactory extends MSFactory
  81. class StreamFifo[T <: Data] extends Component

    First-In-First-Out queue with a push and pop Stream

    First-In-First-Out queue with a push and pop Stream

    - latency of 0, 1, 2 cycles

    Fully redesigned in release 1.8.2 allowing improved timing closure.

    See also

    StreamFifoCC and StreamCCByToggle for cross clock domain FIFOs

  82. class StreamFifoCC[T <: Data] extends Component
  83. trait StreamFifoInterface[T <: Data] extends AnyRef
  84. class StreamFifoLowLatency[T <: Data] extends Component
  85. case class StreamFifoMultiChannelPop[T <: Data](payloadType: HardType[T], channelCount: Int) extends Bundle with IMasterSlave with Product with Serializable
  86. case class StreamFifoMultiChannelPush[T <: Data](payloadType: HardType[T], channelCount: Int) extends Bundle with IMasterSlave with Product with Serializable
  87. case class StreamFifoMultiChannelSharedSpace[T <: Data](payloadType: HardType[T], channelCount: Int, depth: Int, withAllocationFifo: Boolean = false) extends Component with Product with Serializable
  88. class StreamFlowArbiter[T <: Data] extends Area
  89. class StreamFork[T <: Data] extends Component

    A StreamFork will clone each incoming data to all its output streams.

    A StreamFork will clone each incoming data to all its output streams. If synchronous is true, all output streams will always fire together, which means that the stream will halt until all output streams are ready. If synchronous is false, output streams may be ready one at a time, at the cost of an additional flip flop (1 bit per output). The input stream will block until all output streams have processed each item regardlessly.

    Note that this means that when synchronous is true, the valid signal of the outputs depends on their inputs, which may lead to dead locks when used in combination with systems that have it the other way around. It also violates the handshake of the AXI specification (section A3.3.1).

  90. class StreamForkArea[T <: Data] extends Area
  91. class StreamFragmentBitsDispatcher extends Area
  92. case class StreamFragmentBitsDispatcherElement(sink: Stream[Bits], header: Int) extends Product with Serializable
  93. class StreamFragmentBitsPimped extends AnyRef
  94. class StreamFragmentFactory extends MSFactory
  95. class StreamFragmentPimped[T <: Data] extends AnyRef
  96. class StreamMux[T <: Data] extends Component
  97. class StreamPacker[T <: Data] extends Area

    Packs layout's Data into the given stream

    Packs layout's Data into the given stream

    stream is directly driven by this area.

    layout Data is read directly

    io.start indicates when to start packing. All layout's Data is registered before packing.

    io.done indicates when the last word has been packed.

    Use the companion object StreamPacker to create an instance.

  98. trait StreamPipe extends AnyRef
  99. class StreamShiftChain[T <: Data] extends Component
  100. class StreamToStreamFragmentBits[T <: Data] extends Component
  101. class StreamTransactionCounter extends Component
  102. class StreamTransactionExtender[T <: Data, T2 <: Data] extends Component
  103. class StreamUnpacker[T <: Data] extends Area

    Unpacks stream's words into the given layout's Data.

    Unpacks stream's words into the given layout's Data. stream is directly driven by this area. layout Data are driven through a register.

    io.start starts unpacking io.dones is set of bits indicating when the associated Data in layout is unpacked. io.allDone indicates when the last word has been unpacked.

    Use the companion object StreamUnpacker to create an instance.

  104. class StringPimped extends AnyRef
  105. class Timeout extends ImplicitArea[Bool]
  106. class TraversableOnceAddressTransformerPimped extends AnyRef
  107. class TraversableOnceAnyPimped[T] extends AnyRef
  108. class TraversableOnceAnyTuplePimped[T, T2] extends AnyRef
  109. class TraversableOnceBoolPimped extends AnyRef
  110. class TraversableOncePimped[T <: Data] extends AnyRef
  111. implicit class UIntPimper extends AnyRef
  112. case class WhenBuilder() extends Product with Serializable

    Allow for example to add when programmatically in loops.

    Allow for example to add when programmatically in loops.

    See also

    WhenBuilder Documentation

  113. class FlowCCByToggle[T <: Data] extends FlowCCUnsafeByToggle[T]
    Annotations
    @deprecated
    Deprecated

    Renamed to 'UnsafeFlowCCByToggle' because it's not safe in many cases, see its comments

  114. class StreamDispatcherSequencial[T <: Data] extends Component

    Deprecated

    Do not use. Use the companion object or a normal regular StreamMux instead.

Value Members

  1. implicit def AnyPimpedDef[T](that: T): AnyPimped[T]
  2. def Event: Stream[NoData]
  3. def NoData(): NoData
  4. val OHMux: MuxOHImpl

    One-Hot multiplexer

    One-Hot multiplexer

    See also

    one-hot encoding

  5. def ScalaStream: scala.collection.immutable.Stream.type
  6. def StreamArbiterFactory(): StreamArbiterFactory
  7. implicit def boolPimped(that: Bool): BoolPimped
  8. implicit def clockDomainPimped(cd: ClockDomain): ClockDomainPimped
  9. implicit def dataCarrierFragmentBitsPimped(that: DataCarrier[Fragment[Bits]]): DataCarrierFragmentBitsPimped
  10. implicit def dataCarrierFragmentPimped[T <: Data](that: DataCarrier[Fragment[T]]): DataCarrierFragmentPimped[T]
  11. implicit def easyFragment[T <: Data](that: Fragment[T]): T
  12. implicit def flowBitsPimped(that: Flow[Bits]): FlowBitsPimped
  13. implicit def flowFragmentPimped[T <: Data](that: Flow[Fragment[T]]): FlowFragmentPimped[T]
  14. implicit def fragmentFixer[T <: Data](_data: Fragment[T]): DataPimper[Fragment[T]]
  15. implicit def growableAnyPimped[T](that: Growable[T]): GrowableAnyPimped[T]
  16. implicit def memPimped[T <: Data](mem: Mem[T]): MemPimped[T]
  17. def sexport[T <: SpinalTag](h: T): T
  18. def sexport[T](name: String, value: Any): ArrayBuffer[() ⇒ Unit]
  19. def sexport[T](h: Handle[T]): Handle[T]
  20. def sexport[T](named: Handle[T], value: ⇒ Any): ArrayBuffer[() ⇒ Unit]
  21. implicit def streamBitsPimped(that: Stream[Bits]): StreamBitsPimped
  22. implicit def streamBundlePimped[T <: Bundle](that: Stream[T]): StreamBundlePimped[T]
  23. implicit def streamFragmentBitsPimped(that: Stream[Fragment[Bits]]): StreamFragmentBitsPimped
  24. implicit def streamFragmentPimped[T <: Data](that: Stream[Fragment[T]]): StreamFragmentPimped[T]
  25. implicit def stringPimped(that: String): StringPimped
  26. implicit def traversableOnceAddressTransformerPimped(that: TraversableOnce[AddressTransformer]): TraversableOnceAddressTransformerPimped
  27. implicit def traversableOnceAnyPimped[T](that: TraversableOnce[T]): TraversableOnceAnyPimped[T]
  28. implicit def traversableOnceAnyTuplePimped[T, T2](that: TraversableOnce[(T, T2)]): TraversableOnceAnyTuplePimped[T, T2]
  29. implicit def traversableOnceBoolPimped(that: TraversableOnce[Bool]): TraversableOnceBoolPimped
  30. implicit def traversableOncePimped[T <: Data](that: TraversableOnce[T]): TraversableOncePimped[T]
  31. object AddWithCarry
  32. object AnalysisUtils
  33. object BoundaryPolicy
  34. object BufferCC
  35. object Callable
  36. object CheckSocketPort
  37. object Clamp
  38. object ClearCount
  39. object ClockGating
  40. object CountLeadingZeroes

    Counts the number of consecutive zero bits starting from the MSB.

  41. object CountOne
  42. object CountOneOnEach
  43. object CountTrailingZeroes

    Counts the number of consecutive zero bits starting from the LSB.

  44. object Counter

    Creates a counter

    Creates a counter

    See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/utils.html?highlight=counter#counter

  45. object CounterDirection
  46. object CounterFreeRun

    Creates an always running counter

    Creates an always running counter

    See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/utils.html?highlight=counter#counter

  47. object CounterMultiRequest
  48. object CounterUpDown
  49. object DataCarrier
  50. object DataCc

    Will use the BaseType.clockDomain to figure out how to connect 2 signals together (allowed use StreamCCByToggle)

  51. object Delay
  52. object DelayEvent
  53. object DelayWithInit
  54. object DoCmd

    Run command

  55. object DownCounter
  56. object EndiannessSwap

    **************************************************************************** Big-Endian <-> Little-Endian

  57. object Flow extends FlowFactory
  58. object FlowArbiter
  59. object FlowCCUnsafeByToggle
  60. object FlowCmdRsp
  61. object FlowFragmentBitsRouter
  62. object Fragment extends FragmentFactory
  63. object FragmentToBitsStates extends SpinalEnum
  64. object GrayCounter
  65. object HIGHER_FIRST extends SlicesOrder

    Slice with higher bits process first

  66. object History
  67. object HistoryModifyable
  68. object JohnsonCounter

    Creates a Johnson counter (also known as a twisted-ring or Möbius counter): a shift register whose inverted MSB feeds back into the LSB, producing a 2*width-state sequence with only one bit transition per cycle.

  69. object KeepAttribute

    Attribute used to instruct the synthesis tool it should not optimize out some signals

  70. object LOWER_FIRST extends SlicesOrder

    Slice with lower bits process first

  71. object LatencyAnalysis
  72. object LeastSignificantBitSet
  73. object MajorityVote
  74. object Max
  75. object MemWriteCmd extends Serializable
  76. object Min
  77. object MuxOH extends MuxOHImpl
  78. object Napot
  79. object OH
  80. object OHMasking
  81. object OHToUInt
  82. object OhMux extends MuxOHImpl
  83. object OneHotCounter

    Creates a one-hot encoded counter

  84. object PriorityMux
  85. object PropagateOnes
  86. object PulseCCByToggle
  87. object RegFlow
  88. object Repeat
  89. object ResetCtrl
  90. object Reverse
  91. object SetCount
  92. object SetFromFirstOne
  93. object Shift
  94. object Stream extends StreamFactory
  95. object StreamAccessibleFifo
  96. object StreamArbiter
  97. object StreamCCByToggle
  98. object StreamCombinerSequential

    This is equivalent to a StreamMux, but with a counter attached to the port selector.

  99. object StreamDemux

    Demultiplex one stream into multiple output streams, always selecting only one at a time.

  100. object StreamDemuxOh
  101. object StreamDispatcherSequential

    This is equivalent to a StreamDemux, but with a counter attached to the port selector.

  102. object StreamFifo
  103. object StreamFifoCC
  104. object StreamFifoLowLatency
  105. object StreamFifoMultiChannelBench extends App
  106. object StreamFlowArbiter

    Combine a stream and a flow to a new stream.

    Combine a stream and a flow to a new stream. If both input sources fire, the flow will be preferred.

  107. object StreamFork
  108. object StreamFork2
  109. object StreamFork3
  110. object StreamFragmentArbiter
  111. object StreamFragmentArbiterAndHeaderAdder
  112. object StreamFragmentGenerator
  113. object StreamFragmentWidthAdapter
  114. object StreamJoin

    Join multiple streams into one.

    Join multiple streams into one. The resulting stream will only fire if all of them fire, so you may want to buffer the inputs.

  115. object StreamMux

    Multiplex multiple streams into a single one, always only processing one at a time.

  116. object StreamPacker
  117. object StreamPipe

    Allows to define what kind of registering (if any) is inserted in a stream connection

  118. object StreamShiftChain
  119. object StreamTransactionCounter
  120. object StreamTransactionExtender
  121. object StreamUnpacker
  122. object StreamWidthAdapter
  123. object Timeout
  124. object UIntToOh
  125. object UIntToOhMinusOne
  126. object ValidFlow

    Create a new Flow that is always valid, with a given payload

  127. object WrapWithReg
  128. object fromGray
  129. object master extends MS

    Declare a master port

    Declare a master port

    See MS for syntax help.

  130. object slave extends MS

    Declare a slave port

    Declare a slave port

    See MS for syntax help.

  131. object toGray
  132. object whenIndexed
  133. object whenMasked

Deprecated Value Members

  1. object FlowCCByToggle
    Annotations
    @deprecated
    Deprecated

    Renamed to 'UnsafeFlowCCByToggle' because it's not safe in many cases, see its comments

  2. object StreamDispatcherSequencial

    Deprecated

    Do not use

  3. object masterWithNull extends MS
    Annotations
    @deprecated
    Deprecated

    Use apply or port instead: 'val b = master(maybeNull)' or 'val rgb = master port maybeNull'

  4. object slaveWithNull extends MS
    Annotations
    @deprecated
    Deprecated

    Use apply or port instead: 'val b = slave(maybeNull)' or 'val rgb = slave port maybeNull'

Inherited from AnyRef

Inherited from Any

Ungrouped