Packages

t

spinal.lib

IMasterSlave

trait IMasterSlave extends AnyRef

An interface that a Bundle can implement if it obeys to a master/slave topology.

See also

Bundle documentation

Linear Supertypes
AnyRef, Any
Known Subclasses
Flow, FlowCmdRsp, MemReadPort, MemReadPortAsync, MemReadStreamFlowPort, MemReadWritePort, Stream, StreamFifoMultiChannelPop, StreamFifoMultiChannelPush, VJTAG, JtaggIo, Mmcme2Dbus, AhbLite3, AhbLite3Master, Apb3, Apb4, Axi4, Axi4ReadOnly, Axi4Shared, Axi4WriteOnly, AxiLite4, AxiLite4ReadOnly, AxiLite4WriteOnly, AvalonMM, AvalonST, Bmb, BRAM, MemBus, MinBus, AsyncMemoryBus, PipelinedMemoryBus, Bus, ContextBufferQuery, FlushBus, Wishbone, Gmii, GmiiRx, GmiiTx, Mdio, Mii, MiiRx, MiiTx, PhyIo, Rmii, RmiiRx, RmiiTx, MacEthPackets, I2c, I2cSlaveBus, Jtag, JtagTapInstructionCtrl, Sio, SpiHalfDuplexMaster, SpiMaster, SpiSlave, SpiXdrMaster, XipBus, XdrOutput, XdrPin, Uart, UsbHostManagementIo, Ctrl, CtrlPort, CtrlRx, UsbLsFsPhyAbstractIo, UsbPhyFsNativeIo, PhyIo, Rx, Tx, DebugBus, DebugHartBus, DebugSysBus, CoreDataBus, CoreInstructionBus, DataCacheCpuBus, DataCacheMemBus, InstructionCacheCpuBus, InstructionCacheFlushBus, InstructionCacheMemBus, DebugExtensionBus, DebugExtensionIo, Ctrl, Mem, VideoDmaMem, Vga, VgaBus, ReadableOpenDrain, TriState, TriStateArray, TriStateOutput, Dfi, DfiCATrainingInterface, DfiControlInterface, DfiErrorInterface, DfiLevelingTraingInterface, DfiLowPowerControlInterface, DfiPhyRequesetedTrainingInterface, DfiReadInterface, DfiReadTrainingInterface, DfiStatusInterface, DfiUpdateInterface, DfiWriteInterface, DfiWriteTrainingInterface, Dfi, DfiCATrainingInterface, DfiControlInterface, DfiErrorInterface, DfiLevelingTraingInterface, DfiLowPowerControlInterface, DfiPhyRequesetedTrainingInterface, DfiReadInterface, DfiReadTrainingInterface, DfiStatusInterface, DfiUpdateInterface, DfiWriteInterface, DfiWriteTrainingInterface, IDFI, OpTasks, PreTaskPort, TaskPort, SdramCtrlBus, SdramInterface, CorePort, CoreTasks, SdramXdrIo, SdramXdrPhyCtrl, SdramXdrPhyCtrlPhase, SoftBus, RtlPhyInterface, SystemDebuggerMemBus, SystemDebuggerRemoteBus, DmaMemoryCoreReadBus, DmaMemoryCoreWriteBus, SgBus
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. IMasterSlave
  2. AnyRef
  3. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Abstract Value Members

  1. abstract def asMaster(): Unit

    Override it to define port directions for a master interface.

    Override it to define port directions for a master interface.

    Deprecated

    This method must be overriden but not called. Calling this method is not correct. Call setAsMaster() or intoMaster() instead. This method is named asXxx but it does not return Xxx. This method does not update isMasterInterface and isSlaveInterface.

Concrete Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  5. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @IntrinsicCandidate()
  6. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  7. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  8. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  9. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  10. final def intoMaster(): IMasterSlave.this.type

    Convert into master

  11. final def intoSlave(): IMasterSlave.this.type

    Convert into slave

  12. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  13. final def isMasterInterface: Boolean

    Are port directions set for a Master interface?

  14. final def isSlaveInterface: Boolean

    Are port directions set for a Master interface?

  15. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  16. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  17. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  18. final def setAsMaster(): Unit

    Set as master interface

  19. final def setAsSlave(): Unit

    Set a slave interface

  20. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  21. def toString(): String
    Definition Classes
    AnyRef → Any
  22. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  23. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  24. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Deprecated Value Members

  1. def asSlave(): Unit

    Override it to define port directions for a master interface.

    Override it to define port directions for a master interface.

    If not overriden, defaults to the opposite port directions of asMaster().

    Deprecated

    This method can be overriden but not called. Calling this method is not correct. Call setAsSlave() or intoSlave() instead. This method is named asXxx but it does not return Xxx. This method does not update isMasterInterface and isSlaveInterface.

  2. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from AnyRef

Inherited from Any

Ungrouped