class MemPimped[T <: Data] extends AnyRef
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- def flowReadSync[T2 <: Data](cmd: Flow[UInt], linkedData: T2): Flow[ReadRetLinked[T, T2]]
- def flowReadSync(cmd: Flow[UInt]): Flow[T]
- def formalCount(cond: (T) ⇒ Bool): UInt
- def formalCount(word: T): UInt
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- def readAsyncPort(): MemReadPortAsync[T]
- def readAsyncPortBySyncReadRevertedClk: MemReadPortAsync[T]
- def readSyncPort(readUnderWrite: ReadUnderWritePolicy = dontCare, clockCrossing: Boolean = false): MemReadPort[T]
- def readSyncPort: MemReadPort[T]
- def readWriteSyncPort(maskWidth: Int = -1, readUnderWrite: ReadUnderWritePolicy = dontCare, clockCrossing: Boolean = false, duringWrite: DuringWritePolicy = dontCare): MemReadWritePort[T]
- def streamReadSync(cmd: Stream[UInt], crossClock: Boolean): Stream[T]
- def streamReadSync(cmd: Stream[UInt]): Stream[T]
- def streamReadSync[T2 <: Data](cmd: Stream[UInt], linkedData: T2, crossClock: Boolean = false): Stream[ReadRetLinked[T, T2]]
- def streamReadSyncMultiPort(cmd: Seq[Stream[UInt]], crossClock: Boolean = false): Vec[Stream[T]]
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def
writePort(): Flow[MemWriteCmd[T]]
Create a write port of memory.
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def
writePortWithMask(maskWidth: Int): Flow[MemWriteCmdWithMask[T]]
Create a write port of memory with masking.
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