class Stream[T <: Data] extends Bundle with IMasterSlave with DataCarrier[T]
A simple interface with master payload valid
, slave ready
handshake.
When manually reading/driving the signals of a Stream keep in mind that:
- After being asserted,
valid
may only be deasserted once the current payload was acknowledged. This meansvalid
can only toggle to 0 the cycle after a the slave did a read by asserting ready. - In contrast to that
ready
may change at any time. - A transfer is only done on cycles where both
valid
andready
are asserted. valid
of a Stream must not depend onready
in a combinatorial way and any path between the two must be registered.
It is recommended that valid
does not depend on ready
at all.
- See also
- Alphabetic
- By Inheritance
- Stream
- DataCarrier
- IMasterSlave
- Bundle
- ValCallbackRec
- ValCallback
- MultiData
- Data
- InComponent
- OverridedEqualsHashCode
- SpinalTagReady
- Assignable
- NameableByComponent
- Nameable
- OwnableRef
- ContextUser
- ScalaLocated
- GlobalDataUser
- AnyRef
- Any
- Hide All
- Show All
- Public
- All
Type Members
-
abstract
type
RefOwnerType
- Definition Classes
- OwnableRef
Value Members
-
final
def
!=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
def
##(right: Data): Bits
Concatenation between two signals
Concatenation between two signals
- Definition Classes
- Data
-
final
def
##(): Int
- Definition Classes
- AnyRef → Any
-
def
#*(count: Int): Bits
Return the
count
time concatenation of the signal.Return the
count
time concatenation of the signal.- Definition Classes
- Data
- def &(cond: Bool): Stream[T]
-
def
<-/<(that: Stream[T]): Stream[T]
Connect
slaveStream <-/< masterStream
.Connect
slaveStream <-/< masterStream
. Thevalid
/payload
/ready
path are cut by an register stage. -
def
<-<(that: Stream[T]): Stream[T]
Connect
slaveStream <-< masterStream
.Connect
slaveStream <-< masterStream
. Thevalid
/payload
path are cut by an register stage. -
def
</<(that: Stream[T]): Stream[T]
Connect
slaveStream </< masterStream
.Connect
slaveStream </< masterStream
. Theready
path is cut by an register stage. -
def
<<(that: Stream[T]): Stream[T]
Connect
slaveStream << masterStream
without any registering. -
final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
def
>->(into: Stream[T]): Stream[T]
Connect
masterStream >-> slaveStream
.Connect
masterStream >-> slaveStream
. Thevalid
/payload
path are cut by an register stage. -
def
>/->(into: Stream[T]): Stream[T]
Connect
masterStream >/-> slaveStream
.Connect
masterStream >/-> slaveStream
. Thevalid
/payload
/ready
path are cut by an register stage. -
def
>/>(that: Stream[T]): Stream[T]
Connect
masterStream >/> slaveStream
.Connect
masterStream >/> slaveStream
. Theready
path is cut by an register stage. -
def
>>(into: Stream[T]): Stream[T]
Connect
masterStream >> slaveStream
without any registering. -
def
IFparent: Data
- Definition Classes
- Data
-
val
_spinalTags: LinkedHashSet[SpinalTag]
- Definition Classes
- SpinalTagReady
-
def
addAttribute(attribute: Attribute): Stream.this.type
- Definition Classes
- Data → SpinalTagReady
-
def
addAttribute(name: String, value: Int): Stream.this.type
- Definition Classes
- SpinalTagReady
-
def
addAttribute(name: String, value: String): Stream.this.type
- Definition Classes
- SpinalTagReady
-
def
addAttribute(name: String): Stream.this.type
- Definition Classes
- SpinalTagReady
-
def
addFragmentLast(counter: Counter): Stream[Fragment[T]]
Like addFragmentLast(Bool), but instead of manually telling which values go together, let a counter do the job.
Like addFragmentLast(Bool), but instead of manually telling which values go together, let a counter do the job.
The counter will increment for each passing element. Last will be set high at the end of each revolution.
outStream = inStream.addFragmentLast(new Counter(5))
Example: -
def
addFragmentLast(last: Bool): Stream[Fragment[T]]
Convert this Stream to a fragmented Stream by adding a last bit.
-
def
addTag[T <: SpinalTag](spinalTag: T): Stream.this.type
- Definition Classes
- MultiData → SpinalTagReady
-
def
addTags(h: SpinalTag, tail: SpinalTag*): Stream.this.type
- Definition Classes
- SpinalTagReady
-
def
addTags[T <: SpinalTag](tags: Iterable[T]): Stream.this.type
- Definition Classes
- SpinalTagReady
-
def
allowDirectionLessIo(): Stream.this.type
Allow a signal of an io
Bundle
to be directionless.Allow a signal of an io
Bundle
to be directionless.- Definition Classes
- Data
- See also
-
def
allowOverride(): Stream.this.type
Allow a signal to be overridden.
Allow a signal to be overridden.
- Definition Classes
- Data
- See also
-
def
allowPartialyAssigned(): Stream.this.type
Allow a register to be partially assigned
Allow a register to be partially assigned
- Definition Classes
- Data
-
def
allowPruning(): Stream.this.type
- Definition Classes
- Data
-
def
allowSimplifyIt(): Stream.this.type
- Definition Classes
- Data
-
def
allowUnsetRegToAvoidLatch(): Stream.this.type
Allow a register to have only an init (no assignments)
Allow a register to have only an init (no assignments)
- Definition Classes
- Data
- See also
-
def
arbitrationFrom[T2 <: Data](that: Stream[T2]): Unit
Drive arbitration signals of this Stream from the provided Stream
-
def
as[T <: Data](dataType: HardType[T]): T
- Definition Classes
- Data
-
def
asBits: Bits
Cast signal to Bits
-
def
asData: Data
- Definition Classes
- Data
- def asDataStream: Stream[Data]
- def asFlow: Flow[T]
-
def
asInOut(): Stream.this.type
Set a signal as
inout
-
def
asInput(): Stream.this.type
Set a data as input
-
final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
-
def
asOutput(): Stream.this.type
Set a data as output
- def assertPersistence(): Unit
-
def
assignAllByName(that: Bundle): Unit
Assign the bundle with an other bundle by name
Assign the bundle with an other bundle by name
- Definition Classes
- Bundle
-
def
assignDontCare(): Stream.this.type
Assign the default 'x' value to all signals composing this type.
Assign the default 'x' value to all signals composing this type.
- Definition Classes
- Data
- See also
-
def
assignDontCareToUnasigned(): Stream.this.type
- Definition Classes
- Data
- def assignFormalRandom(kind: RandomExpKind): Unit
-
final
def
assignFrom(that: AnyRef, target: AnyRef = this)(implicit loc: Location): Unit
- Definition Classes
- Data
- def assignFromBits(bits: Bits, hi: Int, lo: Int): Unit
- def assignFromBits(bits: Bits): Unit
-
def
assignFromBits(bits: Bits, offset: Int, bitCount: BitCount): Unit
- Definition Classes
- Data
-
def
assignFromImpl(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit
- Attributes
- protected
- Definition Classes
- Bundle → Assignable
-
def
assignSomeByName(that: Bundle): Unit
Assign all possible signal fo the bundle with an other bundle by name
Assign all possible signal fo the bundle with an other bundle by name
- Definition Classes
- Bundle
-
def
assignUnassignedByName(that: MultiData): Unit
- Definition Classes
- MultiData
-
def
bundleAssign(that: Bundle)(f: (Data, Data) ⇒ Unit): Unit
- Definition Classes
- Bundle
- def ccToggle(pushClock: ClockDomain, popClock: ClockDomain): Stream[T]
- def ccToggleInputWait(pushClock: ClockDomain, popClock: ClockDomain): Stream[T]
- def ccToggleWithoutBuffer(pushClock: ClockDomain, popClock: ClockDomain): Stream[T]
-
def
checkDir(that: Bundle): Boolean
for interface find modport
for interface find modport
- Definition Classes
- Bundle
-
def
clearAll(): Stream.this.type
Clear all bits to
and return itselfFalse
Clear all bits to
and return itselfFalse
- Definition Classes
- Data
- def clearValidWhen(cond: Bool): Stream[T]
- def clone(): Stream[T]
-
def
combStage(): Stream[T]
A combinatorial stage doesn't do anything, but it is nice to separate signals for combinatorial transformations.
-
def
component: Component
- Definition Classes
- ContextUser
-
final
def
compositAssignFrom(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit
- Definition Classes
- Assignable
-
val
compositeAssign: Assignable
- Definition Classes
- Assignable
- def connectFrom(that: Stream[T]): Stream[T]
-
def
continueWhen(cond: Bool): Stream[T]
Block this when cond is
False
.Block this when cond is
False
. Return the resulting Stream - def copyDirectionOfImpl(that: Data): Stream.this.type
-
def
delay(cycleCount: Int): Stream[T]
Delay the stream by a given number of cycles.
Delay the stream by a given number of cycles.
- cycleCount
Number of cycles to delay the stream
- returns
Delayed stream
-
def
dirString(): String
- Definition Classes
- Data
-
def
discardWhen(cond: Bool): Stream[T]
Discard transactions when cond is
True
.Discard transactions when cond is
True
.This is the same as throwWhen() but with a semantically clearer function name. Prefer discardWhen() over throwWhen() for new designs.
- cond
Condition
- returns
The resulting Stream
-
def
dontSimplifyIt(): Stream.this.type
- Definition Classes
- Data
- def elements: ArrayBuffer[(String, Data)]
-
var
elementsCache: ArrayBuffer[(String, Data)]
- Definition Classes
- Bundle
-
def
elementsString: String
- Definition Classes
- MultiData
-
final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
def
equals(obj: Any): Boolean
- Definition Classes
- OverridedEqualsHashCode → AnyRef → Any
-
def
existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean
- Definition Classes
- SpinalTagReady
-
def
filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]
- Definition Classes
- SpinalTagReady
-
def
find(name: String): Data
- Definition Classes
- MultiData
-
def
findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]
- Definition Classes
- SpinalTagReady
-
def
fire: Bool
Return
True
when a transaction occurs on the bus (valid && ready
)Return
True
when a transaction occurs on the bus (valid && ready
)- Definition Classes
- Stream → DataCarrier
- def flatten: Seq[BaseType]
- def flattenForeach(body: (BaseType) ⇒ Unit): Unit
- def flattenLocalName: Seq[String]
-
def
flip(): Stream.this.type
Flip the direction of the signal.
-
def
foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit
- Definition Classes
- Nameable
-
def
foreachTag(body: (SpinalTag) ⇒ Unit): Unit
- Definition Classes
- SpinalTagReady
- def forkSerial(cond: Bool): Stream[T]
-
def
formalAssertsMaster(payloadInvariance: Boolean = true)(implicit loc: Location): Composite[Stream[T]] { val stack: String }
Assert that this stream conforms to the stream semantics: https://spinalhdl.github.io/SpinalDoc-RTD/dev/SpinalHDL/Libraries/stream.html#semantics - After being asserted, valid may only be deasserted once the current payload was acknowledged.
Assert that this stream conforms to the stream semantics: https://spinalhdl.github.io/SpinalDoc-RTD/dev/SpinalHDL/Libraries/stream.html#semantics - After being asserted, valid may only be deasserted once the current payload was acknowledged.
- payloadInvariance
Check that the payload does not change when valid is high and ready is low.
- def formalAssertsOrder(dataAhead: T, dataBehind: T)(implicit loc: Location): (Bool, Bool)
-
def
formalAssertsTimeout(maxStallCycles: Int = 0): Composite[Stream[T]] { val logic: spinal.core.Area{val counter: spinal.lib.Counter} }
Assert that this stream conforms to the stream semantics: https://spinalhdl.github.io/SpinalDoc-RTD/dev/SpinalHDL/Libraries/stream.html#semantics - After being asserted, valid should be acknowledged in limited cycles.
Assert that this stream conforms to the stream semantics: https://spinalhdl.github.io/SpinalDoc-RTD/dev/SpinalHDL/Libraries/stream.html#semantics - After being asserted, valid should be acknowledged in limited cycles.
- maxStallCycles
Check that the max cycles the interface would hold in stall.
- def formalAssumesOrder(dataAhead: T, dataBehind: T)(implicit loc: Location): (Bool, Bool)
- def formalAssumesSlave(payloadInvariance: Boolean = true)(implicit loc: Location): Composite[Stream[T]]
- def formalAssumesTimeout(maxStallCycles: Int = 0): Composite[Stream[T]] { val logic: spinal.core.Area{val counter: spinal.lib.Counter} }
- def formalCovers(back2BackCycles: Int = 1): Composite[Stream[T]] { val hist: spinal.core.Bool }
- def fragmentTransaction(bitsWidth: Int): Stream[Fragment[Bits]]
-
def
freeRun(): Stream.this.type
- Definition Classes
- Stream → DataCarrier
- def freeze(): Stream.this.type
-
def
getAheadValue(): Stream.this.type
For a register, get the value it will have at the next clock, as a combinational signal.
For a register, get the value it will have at the next clock, as a combinational signal.
- Definition Classes
- Data
-
def
getBitsWidth: Int
Return the width of the data
-
final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
-
def
getComponent(): Component
- Definition Classes
- Data → InComponent → NameableByComponent
-
def
getComponents(): Seq[Component]
Get current component with all parents
Get current component with all parents
- Definition Classes
- InComponent
-
def
getDirection: IODirection
- Definition Classes
- Data
-
def
getDisplayName(): String
- Definition Classes
- Nameable
-
def
getInstanceCounter: Int
- Definition Classes
- ContextUser
-
def
getMode: Byte
- Attributes
- protected
- Definition Classes
- Nameable
-
def
getMuxType[T <: Data](list: TraversableOnce[T]): HardType[T]
- Definition Classes
- Data
-
def
getName(default: String): String
- Definition Classes
- NameableByComponent → Nameable
-
def
getName(): String
- Definition Classes
- NameableByComponent → Nameable
-
def
getPartialName(): String
- Definition Classes
- Nameable
-
def
getPath(from: Component, to: Component): Seq[Component]
- Definition Classes
- NameableByComponent
-
def
getRealSource: Any
- Definition Classes
- Assignable
-
def
getRealSourceNoRec: Any
- Definition Classes
- Data → Assignable
-
def
getRefOwnersChain(): List[Any]
- Definition Classes
- OwnableRef
-
def
getRootParent: Data
- Definition Classes
- Data
-
def
getRtlPath(separator: String = "/"): String
- Definition Classes
- Data
-
def
getScalaLocationLong: String
- Definition Classes
- ScalaLocated
-
def
getScalaLocationShort: String
- Definition Classes
- ScalaLocated
-
def
getScalaTrace(): Throwable
- Definition Classes
- ScalaLocated
-
def
getTag[T <: SpinalTag](clazz: Class[T]): Option[T]
- Definition Classes
- SpinalTagReady
-
def
getTags(): LinkedHashSet[SpinalTag]
- Definition Classes
- SpinalTagReady
-
def
getTagsOf[T <: SpinalTag]()(implicit tag: ClassTag[T]): Iterable[T]
- Definition Classes
- SpinalTagReady
- def getTypeString: String
-
def
getZero: Stream.this.type
Create a signal set to 0
-
val
globalData: GlobalData
- Definition Classes
- GlobalDataUser
-
def
halfPipe(flush: Bool = null, keep: Boolean = false): Stream[T]
Return a Stream that cut all path, but divide the bandwidth by 2.
Return a Stream that cut all path, but divide the bandwidth by 2.
The cost is
(payload width + 2)
flip-flops and the latency is 1. -
def
haltWhen(cond: Bool): Stream[T]
Stop transactions on this when cond is
True
and return the resulting Stream. -
var
hardtype: HardType[_]
- Definition Classes
- Bundle
-
def
hasTag[T <: SpinalTag](clazz: Class[T]): Boolean
- Definition Classes
- SpinalTagReady
-
def
hasTag(spinalTag: SpinalTag): Boolean
- Definition Classes
- SpinalTagReady
-
def
hashCode(): Int
- Definition Classes
- OverridedEqualsHashCode → AnyRef → Any
-
final
def
initFrom(that: AnyRef, target: AnyRef = this): Unit
- Definition Classes
- Data
-
def
instanceAttributes(language: Language): Iterable[Attribute]
- Definition Classes
- SpinalTagReady
-
def
instanceAttributes: Iterable[Attribute]
- Definition Classes
- SpinalTagReady
-
final
def
intoMaster(): Stream.this.type
Convert into master
Convert into master
- Definition Classes
- IMasterSlave
-
final
def
intoSlave(): Stream.this.type
Convert into slave
Convert into slave
- Definition Classes
- IMasterSlave
-
def
isAnalog: Boolean
- Definition Classes
- Data
-
def
isComb: Boolean
- Definition Classes
- Data
-
def
isCompletelyUnnamed: Boolean
- Definition Classes
- Nameable
-
def
isDirectionLess: Boolean
- Definition Classes
- Data
-
def
isEmptyOfTag: Boolean
- Definition Classes
- SpinalTagReady
-
def
isFree: Bool
Return
True
when the bus isn't stuck with a transaction (!isStall
) -
def
isInOut: Boolean
- Definition Classes
- Data
-
def
isInput: Boolean
- Definition Classes
- Data
-
def
isInputOrInOut: Boolean
- Definition Classes
- Data
-
final
def
isInstanceOf[T0]: Boolean
- Definition Classes
- Any
-
final
def
isMasterInterface: Boolean
Are port directions set for a Master interface?
Are port directions set for a Master interface?
- Definition Classes
- IMasterSlave
-
final
def
isNamed: Boolean
- Definition Classes
- Nameable
-
def
isNew: Bool
Return
True
when a transaction has appeared (first cycle) -
def
isOutput: Boolean
- Definition Classes
- Data
-
def
isOutputOrInOut: Boolean
- Definition Classes
- Data
-
def
isPriorityApplicable(namePriority: Byte): Boolean
- Definition Classes
- Nameable
-
def
isReg: Boolean
- Definition Classes
- Data
-
def
isRegOnAssign: Boolean
- Definition Classes
- Data
-
final
def
isSlaveInterface: Boolean
Are port directions set for a Master interface?
Are port directions set for a Master interface?
- Definition Classes
- IMasterSlave
-
def
isStall: Bool
Return
True
when a transaction is present on the bus but theready
signal is low -
def
isUnnamed: Boolean
- Definition Classes
- NameableByComponent → Nameable
-
def
m2sPipe(collapsBubble: Boolean = true, crossClockData: Boolean = false, flush: Bool = null, holdPayload: Boolean = false, keep: Boolean = false, initPayload: ⇒ T = null.asInstanceOf[T]): Stream[T]
Return a stream that cut the
valid
andpayload
signals through registers.Return a stream that cut the
valid
andpayload
signals through registers.The cost is
(payload width + 1)
flip-flops and the latency is 1.The name "m2s" comes from from the fact that the signals that flow from Master-to-Slave are pipelined (namely
ready
andpayload
).- collapsBubble
When
true
(the default), add the logic to allow to store an incoming payload when there is no stored payload and the slave is not ready.- crossClockData
If
false
(the default), do not add tags on the payload signal for clock domain crossing.- flush
An optional signal to set the
valid
register to 0.- holdPayload
When
false
(the default), do not add the logic to keep the slave side payload constant after the one cycle when the slave consumed the payload.- keep
If
false
(the default), do not add an attribute to avoid optimization of the slave side valid and payload.- initPayload
If not
null
, a value to initialize the payload registers.
- See also
stage()
-
def
map[T2 <: Data](translate: (T) ⇒ T2): Stream[T2]
Return a Stream with payload calculated by a translate function.
Return a Stream with payload calculated by a translate function.
Modify the payload of the x stream, while preserving the valid and ready signals
-
val
name: String
- Definition Classes
- Nameable
- val nameableRef: Nameable
-
final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
def
noBackendCombMerge(): Stream.this.type
Put the combinatorial logic driving this signal in a separate process
Put the combinatorial logic driving this signal in a separate process
- Definition Classes
- Data
-
def
noCombLoopCheck(): Stream.this.type
Disable combinatorial loop checking for this Data
Disable combinatorial loop checking for this Data
- Definition Classes
- Data
- See also
-
final
def
notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
-
final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
-
def
onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit
- Definition Classes
- SpinalTagReady
-
def
overrideLocalName(name: String): Stream.this.type
- Definition Classes
- Nameable
-
val
parent: Data
- Definition Classes
- Data
-
val
parentScope: ScopeStatement
- Definition Classes
- ContextUser
-
val
payload: T
Content of the transaction driven by the master, don't care when
valid
is 0.Content of the transaction driven by the master, don't care when
valid
is 0.- Definition Classes
- Stream → DataCarrier
- val payloadType: HardType[T]
-
def
pipelined(m2s: Boolean = false, s2m: Boolean = false, halfRate: Boolean = false): Stream[T]
Return a pipelined version of this Stream based on the provided arguments.
-
def
pipelined(pipe: StreamPipe): Stream[T]
Return a pipelined version of this Stream based on the provided StreamPipe spec.
-
def
pull(propagateName: Boolean): Stream.this.type
- Definition Classes
- Data
-
def
pull(): Stream.this.type
Pull a signal to the top level (use for debugging)
Pull a signal to the top level (use for debugging)
- Definition Classes
- Data
-
def
purify(): Stream.this.type
- Definition Classes
- Data
-
def
queue(size: Int, pushClock: ClockDomain, popClock: ClockDomain): Stream[T]
Connect this to an clock crossing fifo and return its pop stream
-
def
queue(size: Int, latency: Int = 2, forFMax: Boolean = false): Stream[T]
Connect this to a fifo and return its pop stream
-
def
queueLowLatency(size: Int, latency: Int = 0): Stream[T]
Connect this to a zero latency fifo and return its pop stream
-
def
queueOfReg(size: Int, latency: Int = 1, forFMax: Boolean = false, initPayload: ⇒ Option[T] = None): Stream[T]
Connect this to a register constructed fifo and return its pop stream
- def queueWithAvailability(size: Int, latency: Int = 2, forFMax: Boolean = false): (Stream[T], UInt)
-
def
queueWithOccupancy(size: Int, latency: Int = 2, forFMax: Boolean = false): (Stream[T], UInt)
Connect this to a fifo and return its pop stream and its occupancy
-
def
queueWithPushOccupancy(size: Int, pushClock: ClockDomain, popClock: ClockDomain): (Stream[T], UInt)
Connect this to a cross clock domain fifo and return its pop stream and its push side occupancy
-
def
randBoot(u: Unit): Stream.this.type
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
- Definition Classes
- Data
-
val
ready: Bool
Signal driven by the slave, indicating consumption of the
payload
, don't care whenvalid
is 0. -
val
refOwner: RefOwnerType
- Definition Classes
- OwnableRef
- Annotations
- @DontName()
-
def
reflectNames(): Unit
- Definition Classes
- Nameable
-
def
removeAssignments(data: Boolean = true, init: Boolean = true, initial: Boolean = true): Stream.this.type
- Definition Classes
- Data
-
def
removeDataAssignments(): Stream.this.type
- Definition Classes
- Data
-
def
removeInitAssignments(): Stream.this.type
- Definition Classes
- Data
-
def
removeTag(spinalTag: SpinalTag): Stream.this.type
- Definition Classes
- SpinalTagReady
-
def
removeTags(tags: Iterable[SpinalTag]): Stream.this.type
- Definition Classes
- SpinalTagReady
-
def
repeat(times: Int): (Stream[T], UInt)
Connect this to a new stream that only advances every n elements, thus repeating the input several times.
Connect this to a new stream that only advances every n elements, thus repeating the input several times.
- returns
A tuple with the resulting stream that duplicates the items and the counter, indicating how many times the current element has been repeated.
-
def
resized: Stream.this.type
Return a version of the signal which is allowed to be automatically resized where needed.
Return a version of the signal which is allowed to be automatically resized where needed.
The resize operation is deferred until the point of assignment later. The resize may widen or truncate, retaining the LSB.
- Definition Classes
- Data
- See also
-
def
rootIF(): Interface
root interface
root interface
- Definition Classes
- Data
-
def
rootIFList(): List[Interface]
- Definition Classes
- Data
-
def
rootIFrec(now: Data, lastRoot: List[Interface]): List[Interface]
- Definition Classes
- Data
- def s2mPipe(stagesCount: Int): Stream[T]
-
def
s2mPipe(flush: Bool = null, keep: Boolean = false, savePower: Boolean = false): Stream[T]
Return a stream that cut the
ready
path through a register.Return a stream that cut the
ready
path through a register.As long as the slave is ready, the
valid
andpayload
signal are passed without registering. When the slaveready
goes to low, the payload is stored and will be consumed later at the first cycle ofready
to high.The cost is
payload width + 1
flip-flops andpayload width
mux2. The latency is 0.The name "s2m" comes from from the fact that the signal that flows from Slave-to-Master is pipelined (namely
valid
).- flush
An optional signal to set the
valid
register to 0.- keep
If
false
(the default), do not add an attribute to avoid optimization of the slave side valid and payload signals.
- See also
-
val
scalaTrace: Throwable
- Definition Classes
- ScalaLocated
-
def
setAll(): Stream.this.type
Set all bits to
and return itselfTrue
Set all bits to
and return itselfTrue
- Definition Classes
- Data
-
def
setAsAnalog(): Stream.this.type
- Definition Classes
- Data
-
def
setAsComb(): Stream.this.type
Set baseType to Combinatorial
-
def
setAsDirectionLess(): Stream.this.type
Remove the direction (
in
,out
,inout
) to a signal -
final
def
setAsMaster(): Unit
Set as master interface
Set as master interface
- Definition Classes
- IMasterSlave
-
def
setAsReg(): Stream.this.type
Set baseType to reg
-
final
def
setAsSlave(): Unit
Set a slave interface
Set a slave interface
- Definition Classes
- IMasterSlave
- def setBlocked(): Stream.this.type
-
def
setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): Stream.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): Stream.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, postfix: String): Stream.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, namePriority: Byte): Stream.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, weak: Boolean): Stream.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable): Stream.this.type
- Definition Classes
- Nameable
- def setIdle(): Stream.this.type
-
def
setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): Stream.this.type
- Definition Classes
- Nameable
-
def
setName(name: String, namePriority: Byte): Stream.this.type
- Definition Classes
- Nameable
-
def
setName(name: String, weak: Boolean): Stream.this.type
- Definition Classes
- Nameable
-
def
setName(name: String): Stream.this.type
- Definition Classes
- Nameable
-
def
setNameAsWeak(): Stream.this.type
- Definition Classes
- Nameable
-
def
setOutputAsReg(): Stream.this.type
Recursively set baseType to reg only for output
Recursively set baseType to reg only for output
- Definition Classes
- Data
-
def
setPartialName(name: String, namePriority: Byte, owner: Any): Stream.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String, namePriority: Byte): Stream.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String, weak: Boolean): Stream.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String, namePriority: Byte): Stream.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String, weak: Boolean): Stream.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String): Stream.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String): Stream.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable): Stream.this.type
- Definition Classes
- Nameable
-
def
setRefOwner(that: Any): Unit
- Definition Classes
- OwnableRef
-
def
setScalaLocated(source: ScalaLocated): Stream.this.type
- Definition Classes
- ScalaLocated
-
def
setWeakName(name: String): Stream.this.type
- Definition Classes
- Nameable
-
def
slowdown(factor: Int): Stream[Vec[T]]
Connect this to a new stream whose payload is n times as wide, but that only fires every n cycles.
Connect this to a new stream whose payload is n times as wide, but that only fires every n cycles. It introduces 0 to factor-1 cycles of latency. Mapping a stream into memory and mapping a slowed down stream into memory should yield the same result, thus the elements of the input will be written from high bits to low bits.
-
def
spinalTags: LinkedHashSet[SpinalTag]
- Definition Classes
- SpinalTagReady
-
def
stage(): Stream[T]
Connect this to a valid/payload register stage and return its output stream.
Connect this to a valid/payload register stage and return its output stream.
The cost is
(payload width + 1)
flip-flops and the latency is 1.Equivalent to m2sPipe() but with "stage" name in the generated HDL.
- See also
- def swapPayload[T2 <: Data](that: HardType[T2]): Stream[T2]
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
-
def
takeWhen(cond: Bool): Stream[T]
Drop transaction of this when cond is
False
and return the resulting Stream. -
def
throwWhen(cond: Bool): Stream[T]
Drop transactions of this when cond is
True
and return the resulting Stream. -
def
toEvent(): Event
Ignore the payload
-
def
toFlow: Flow[T]
- returns
Return a flow driven by this stream. Ready of ths stream is always high
- def toFlowFire: Flow[T]
-
def
toIo(): Stream.this.type
- Definition Classes
- Data
-
def
toMuxInput[T <: Data](muxOutput: T): T
- Definition Classes
- Data
- def toReg(init: T): T
- def toReg(): T
- def toString(): String
- def translateFrom[T2 <: Data](that: Stream[T2])(dataAssignment: (T, payload.type) ⇒ Unit): Stream[T]
- def translateInto[T2 <: Data](into: Stream[T2])(dataAssignment: (T2, T) ⇒ Unit): Stream[T2]
-
def
translateWith[T2 <: Data](that: T2): Stream[T2]
Replace this stream's payload with another one
-
def
transmuteWith[T2 <: Data](that: HardType[T2]): Stream[T2]
Change the payload's content type.
Change the payload's content type. The new type must have the same bit length as the current one.
- def unfreeze(): Stream.this.type
-
def
unsetName(): Stream.this.type
- Definition Classes
- Nameable
-
def
valCallback[T](ref: T, name: String): T
- Definition Classes
- ValCallbackRec → ValCallback
-
def
valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit
- Definition Classes
- ValCallbackRec
-
def
valCallbackRec(ref: Any, name: String): Unit
- Definition Classes
- Bundle → ValCallbackRec
-
val
valid: Bool
Signal driven by the master, indicating
payload
present on the interface.Signal driven by the master, indicating
payload
present on the interface.- Definition Classes
- Stream → DataCarrier
- def validPipe(keep: Boolean = false): Stream[T]
-
final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
final
def
wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native()
-
final
def
wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
def
wrapNext(): Stream.this.type
- Definition Classes
- Data
-
def
zipByName(that: MultiData, rec: ArrayBuffer[(BaseType, BaseType)] = ArrayBuffer()): ArrayBuffer[(BaseType, BaseType)]
- Definition Classes
- MultiData
- def ~[T2 <: Data](that: T2): Stream[T2]
- def ~~[T2 <: Data](translate: (T) ⇒ T2): Stream[T2]
Deprecated Value Members
-
def
asDirectionLess(): Stream.this.type
- Definition Classes
- Data
- Annotations
- @deprecated
- Deprecated
(Since version ???) use setAsDirectionLess instead
-
def
asMaster(): Unit
Override it to define port directions for a master interface.
Override it to define port directions for a master interface.
- Definition Classes
- Stream → IMasterSlave
- Deprecated
This method must be overriden but not called. Calling this method is not correct. Call
setAsMaster()
orintoMaster()
instead. This method is namedasXxx
but it does not returnXxx
. This method does not updateisMasterInterface
andisSlaveInterface
.
-
def
asSlave(): Unit
Override it to define port directions for a master interface.
Override it to define port directions for a master interface.
If not overriden, defaults to the opposite port directions of
asMaster()
.- Definition Classes
- IMasterSlave
- Deprecated
This method can be overriden but not called. Calling this method is not correct. Call
setAsSlave()
orintoSlave()
instead. This method is namedasXxx
but it does not returnXxx
. This method does not updateisMasterInterface
andisSlaveInterface
.
-
def
finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( classOf[java.lang.Throwable] ) @Deprecated
- Deprecated
-
def
genIf(cond: Boolean): Stream.this.type
Generate this if condition is true
Generate this if condition is true
- Definition Classes
- Data
- Annotations
- @deprecated
- Deprecated
does not work with <>, use 'someBool generate Type()' or 'if(condition) Type() else null' instead