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t

spinal.core

Assignable

trait Assignable extends AnyRef

Assignable trait

Linear Supertypes
AnyRef, Any
Known Subclasses
AFix, BaseType, BitVector, Bits, Bool, BoolEdges, Bundle, BundleCase, Data, DataWrapper, HardMap, Interface, MemWritePayload, MultiData, SFix, SFix2D, SInt, SpinalEnumCraft, SpinalStruct, TupleBundle1, TupleBundle10, TupleBundle11, TupleBundle12, TupleBundle13, TupleBundle14, TupleBundle15, TupleBundle16, TupleBundle17, TupleBundle18, TupleBundle19, TupleBundle2, TupleBundle20, TupleBundle21, TupleBundle22, TupleBundle3, TupleBundle4, TupleBundle5, TupleBundle6, TupleBundle7, TupleBundle8, TupleBundle9, TupleBundleBase, UFix, UFix2D, UInt, UInt2D, Union, Vec, VecAccessAssign, XFix, Flow, FlowCmdRsp, Fragment, MemReadPort, MemReadPortAsync, MemReadStreamFlowPort, MemReadWritePort, MemWriteCmd, MemWriteCmdWithMask, NoData, PackedBundle, PackedWordBundle, ReadRetLinked, Stream, StreamDelayWord, StreamFifoMultiChannelPop, StreamFifoMultiChannelPush, VJTAG, JtaggIo, Mmcme2Dbus, AhbLite3, AhbLite3Master, Apb3, Cmd, Rsp, Apb4, Axi4, Axi4Ar, Axi4ArUnburstified, Axi4Arw, Axi4ArwUnburstified, Axi4Aw, Axi4AwUnburstified, Axi4Ax, Axi4AxUnburstified, Axi4B, Axi4R, Axi4ReadOnly, Context, Context, RspContext, Axi4Shared, Axi4W, Axi4WriteOnly, Context, WCmd, Context, FormalAxi4Record, IdLen, IdResp, AxiLite4, AxiLite4Ax, AxiLite4B, AxiLite4R, AxiLite4ReadOnly, AxiLite4SimpleReadDmaCmd, AxiLite4W, AxiLite4WriteOnly, Axi4StreamBundle, AvalonMM, AvalonReadDmaCmd, AvalonST, AvalonSTPayload, Bmb, BmbAck, Context, BmbCmd, Ctx, SourceHistory, OutputContext, BmbInv, Context, Context, BmbRsp, Context, BmbSync, Context, Info, Info, Context, OutputContext, BRAM, BsbTransaction, MemBus, MinBus, AsyncMemoryBus, PipelinedMemoryBus, PipelinedMemoryBusCmd, PipelinedMemoryBusRsp, Bus, BusFragment, ChannelA, ChannelB, ChannelC, ChannelD, ChannelE, ContextBufferAdd, ContextBufferQuery, ContextBufferRemove, CtrlCmd, CtxDownD, ProberCmd, PutMergeCmd, ReadBackendCmd, ReadDownCmd, Tags, WriteBackendCmd, DataPayload, CtxA, CtxC, DataPayload, ProbeCmd, ProbeCtx, ProbeCtxFull, OrderingCmd, Wishbone, Gmii, GmiiRx, GmiiTx, MacEthCtrl, Mdio, Mii, MiiRx, MiiTx, PhyIo, PhyRx, PhyTx, Rmii, RmiiRx, RmiiTx, MacEthPackets, MacEthSgCtrl, I2c, I2cAddress, I2cSlaveBus, I2cSlaveCmd, I2cSlaveConfig, I2cSlaveIo, I2cSlaveRsp, Jtag, JtagTapInstructionCtrl, Sio, SpiHalfDuplexMaster, SpiKind, SpiMaster, SpiMasterCmd, SpiMasterCtrlCmdData, SpiMasterCtrlCmdSs, SpiMasterCtrlConfig, SpiSlave, SpiSlaveCtrlIo, SpiXdrMaster, SpiIce40, Cmd, Config, Rsp, XipBus, XipCmd, XdrOutput, XdrPin, Uart, UartCtrlConfig, UartCtrlFrameConfig, UartCtrlIo, UsbHostManagementIo, Ctrl, CtrlPort, CtrlRx, CtrlRxPayload, UsbLsFsPhyAbstractIo, UsbPhyFsNativeIo, PhyIo, Rx, Tx, DebugBus, DebugCapture, DebugCmd, DebugDmToHart, DebugHartBus, DebugHartToDm, DebugRsp, DebugUpdate, BranchPredictorLine, CoreDataBus, CoreDataCmd, CoreDecodeOutput, CoreExecute0Output, CoreExecute1Output, CoreFetchOutput, CoreInstructionBus, CoreInstructionCmd, CoreInstructionRsp, CoreWriteBack0Output, LineInfo, DataCacheCpuBus, DataCacheCpuCmd, DataCacheCpuRsp, DataCacheMemBus, DataCacheMemCmd, DataCacheMemRsp, LineInfo, InstructionCacheCpuBus, InstructionCacheCpuCmd, InstructionCacheCpuRsp, InstructionCacheFlushBus, InstructionCacheMemBus, InstructionCacheMemCmd, InstructionCacheMemRsp, InstructionCtrl, DebugExtensionBus, DebugExtensionCmd, DebugExtensionIo, DebugExtensionRsp, ApbCmd, Ctrl, CtrlCmd, Mem, MemCmd, SblCmd, SblReadCmd, SblReadDmaCmd, SblReadRet, SblWriteCmd, SerialCheckerPhysical, SerialLinkRxToTx, Floating, FloatingCompareResult, RecFloating, Rgb, VideoDmaMem, Ycbcr, YcbcrPix2, Word, Vga, VgaBus, VgaTimings, VgaTimingsHV, D, E, ReadableOpenDrain, TriState, TriStateArray, TriStateOutput, MixedDividerCmd, MixedDividerRsp, SignedDividerCmd, SignedDividerRsp, UnsignedDividerCmd, UnsignedDividerRsp, Dfi, DfiCATrainingInterface, DfiControlInterface, DfiErrorInterface, DfiLevelingTraingInterface, DfiLowPowerControlInterface, DfiPhyRequesetedTrainingInterface, DfiRd, DfiRdCs, DfiReadInterface, DfiReadTrainingInterface, DfiStatusInterface, DfiUpdateInterface, DfiWr, DfiWriteInterface, DfiWriteTrainingInterface, Context, PackContext, Status, Context, PipelineRsp, BusAddress, Dfi, DfiAddr, DfiCATrainingInterface, DfiCmd, DfiControlInterface, DfiError, DfiErrorInterface, DfiInit, DfiLevelingTraingInterface, DfiLowPowerControlInterface, DfiLp, DfiLpCtrl, DfiOdt, DfiPhyLvlCs, DfiPhyRequesetedTrainingInterface, DfiPhyUp, DfiRd, DfiRdCs, DfiRdData, DfiRdGate, DfiRdGateCs, DfiRdLvl, DfiRdLvlCs, DfiReadCs, DfiReadInterface, DfiReadTrainingInterface, DfiStatusInterface, DfiUpdateInterface, DfiWr, DfiWrCs, DfiWrData, DfiWrLvl, DfiWrLvlCs, DfiWriteInterface, DfiWriteTrainingInterface, IDFI, OpTasks, PreTaskPort, SdramAddress, TaskPort, TaskRsp, TaskTimingConfig, TaskWrRdCmd, TaskWriteData, Context, SdramCtrlAxi4SharedContext, SdramCtrlBackendCmd, SdramCtrlBank, SdramCtrlBus, SdramCtrlCmd, SdramCtrlRsp, SdramInterface, PipelineCmd, PipelineRsp, Context, CoreCmd, CoreConfig, CorePort, CoreRsp, CoreTask, CoreTasks, CoreWriteData, InitCmd, SdramAddress, SdramXdrIo, SdramXdrPhyCtrl, SdramXdrPhyCtrlPhase, SoftBus, Status, Task, Address, RtlPhyInterface, RtlPhyWriteCmd, Request, PinsecTimerCtrlExternal, SystemDebuggerMemBus, SystemDebuggerMemCmd, SystemDebuggerRemoteBus, SystemDebuggerRsp, BankWord, DmaMemoryCoreReadBus, DmaMemoryCoreReadCmd, DmaMemoryCoreReadRsp, DmaMemoryCoreWriteBus, DmaMemoryCoreWriteCmd, DmaMemoryCoreWriteRsp, AggregatorCmd, AggregatorRsp, ChannelIo, B2sReadContext, InputContext, M2bWriteContext, ReadContext, SgReadContext, SgWriteContext, WriteContext, SgBus, SgCmd, SgRsp, Word, Word, PopDescriptor
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Visibility
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Abstract Value Members

  1. abstract def getRealSourceNoRec: Any

Concrete Value Members

  1. final def compositAssignFrom(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit
  2. val compositeAssign: Assignable
  3. def getRealSource: Any