package sim
Simulation package
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Type Members
- class CoreSimManager extends SimManager
-
abstract
class
RandomizableBitVector extends AnyRef
- Attributes
- protected
- implicit class SimAFixPimper extends AnyRef
- implicit class SimArrayBufferPimper[T] extends AnyRef
-
implicit
class
SimBaseTypePimper extends AnyRef
Add implicit function to BaseType for simulation
-
implicit
class
SimBigIntPimper extends AnyRef
Add implicit function to BigInt
-
implicit
class
SimBitVectorPimper extends AnyRef
Add implicit function to BitVector
-
implicit
class
SimBitsPimper extends RandomizableBitVector
Add implicit function to Bits
-
implicit
class
SimBoolPimper extends SimEquiv
Add implicit function to Bool
- implicit class SimClockDomainHandlePimper extends SimClockDomainPimper
-
implicit
class
SimClockDomainPimper extends AnyRef
Add implicit function to ClockDomain
-
abstract
class
SimCompiled[T <: Component] extends AnyRef
Run simulation
-
case class
SimConfigLegacy[T <: Component](_rtlGen: Option[() ⇒ T] = None, _spinalConfig: SpinalConfig = SpinalConfig(), _spinalReport: Option[SpinalReport[T]] = None) extends Product with Serializable
Legacy simulation configuration
-
implicit
class
SimDataPimper[T <: Data] extends AnyRef
Add implicit function to Data
-
implicit
class
SimEnumPimper[T <: SpinalEnum] extends SimEquiv
Add implicit function to Enum
-
trait
SimEquiv extends AnyRef
Represents the relationship where a SpinalHDL type can be converted to a certain Scala type during simulation and vice-versa.
- implicit class SimEquivBitVectorBigIntPimper extends SimEquiv
- implicit class SimEquivBitVectorBooleansPimper extends SimEquiv
- implicit class SimEquivBitVectorBytesPimper extends SimEquiv
- implicit class SimEquivBitVectorLongPimper extends SimEquiv
- implicit class SimEquivVecSeqPimper[T <: Data, E] extends SimEquiv
-
abstract
class
SimFix[T <: XFix[_, _]] extends AnyRef
Add implicit function to UFix/SFix/AFix
- implicit class SimMemPimper[T <: Data] extends AnyRef
- case class SimMutex(randomized: Boolean = false) extends Product with Serializable
- implicit class SimSFixPimper extends SimFix[SFix]
-
implicit
class
SimSIntPimper extends RandomizableBitVector
Add implicit function to SInt
- implicit class SimSeqPimper[T] extends AnyRef
- implicit class SimUFixPimper extends SimFix[UFix]
-
implicit
class
SimUIntPimper extends RandomizableBitVector
Add implicit function to UInt
- implicit class SimUnionElementPimper[T <: Data] extends AnyRef
- class SimVerilatorPhase extends PhaseNetlist
- implicit class SimpComponentPimper[T <: Component] extends AnyRef
- case class SpinalGhdlBackendConfig[T <: Component](rtl: SpinalReport[T], waveFormat: WaveFormat = WaveFormat.NONE, workspacePath: String = "./", workspaceName: String = null, wavePath: String = null, wavePrefix: String = null, waveDepth: Int = 0, optimisationLevel: Int = 2, simulatorFlags: ArrayBuffer[String] = ArrayBuffer[String](), runFlags: ArrayBuffer[String] = ArrayBuffer[String](), usePluginsCache: Boolean = true, pluginsCachePath: String = "./simWorkspace/.pluginsCachePath", enableLogging: Boolean = false, timePrecision: TimeNumber = null, ghdlFlags: GhdlFlags = GhdlFlags(), testPath: String = null) extends SpinalVpiBackendConfig[T] with Product with Serializable
- case class SpinalIVerilogBackendConfig[T <: Component](rtl: SpinalReport[T], waveFormat: WaveFormat = WaveFormat.NONE, workspacePath: String = "./", workspaceName: String = null, wavePath: String = null, wavePrefix: String = null, waveDepth: Int = 0, optimisationLevel: Int = 2, simulatorFlags: ArrayBuffer[String] = ArrayBuffer[String](), runFlags: ArrayBuffer[String] = ArrayBuffer[String](), usePluginsCache: Boolean = true, pluginsCachePath: String = "./simWorkspace/.pluginsCachePath", enableLogging: Boolean = false, timePrecision: TimeNumber = null, testPath: String = null) extends SpinalVpiBackendConfig[T] with Product with Serializable
- class SpinalSimBackendSel extends AnyRef
-
case class
SpinalSimConfig(_workspacePath: String = ..., _workspaceName: String = null, _waveDepth: Int = 0, _spinalConfig: SpinalConfig = SpinalConfig(), _optimisationLevel: Int = 0, _simulatorFlags: ArrayBuffer[String] = ArrayBuffer[String](), _runFlags: ArrayBuffer[String] = ArrayBuffer[String](), _additionalRtlPath: ArrayBuffer[String] = ArrayBuffer[String](), _additionalIncludeDir: ArrayBuffer[String] = ArrayBuffer[String](), _waveFormat: WaveFormat = WaveFormat.NONE, _backend: SpinalSimBackendSel = SpinalSimBackendSel.VERILATOR, _withCoverage: Boolean = false, _maxCacheEntries: Int = 100, _cachePath: String = null, _disableCache: Boolean = false, _withLogging: Boolean = false, _vcsCC: Option[String] = None, _vcsLd: Option[String] = None, _vcsUserFlags: VCSFlags = VCSFlags(), _vcsSimSetupFile: String = null, _vcsEnvSetup: () ⇒ Unit = null, _xciSourcesPaths: ArrayBuffer[String] = ArrayBuffer[String](), _bdSourcesPaths: ArrayBuffer[String] = ArrayBuffer[String](), _xilinxDevice: String = "xc7vx485tffg1157-1", _simScript: String = null, _timePrecision: TimeNumber = null, _timeScale: TimeNumber = null, _testPath: String = "$WORKSPACE/$COMPILED/$TEST", _waveFilePrefix: String = null, _ghdlFlags: GhdlFlags = GhdlFlags()) extends Product with Serializable
SpinalSim configuration
- case class SpinalVCSBackendConfig[T <: Component](rtl: SpinalReport[T], waveFormat: WaveFormat = WaveFormat.NONE, workspacePath: String = "./", workspaceName: String = null, wavePath: String = null, wavePrefix: String = null, waveDepth: Int = 0, optimisationLevel: Int = 2, simulatorFlags: ArrayBuffer[String] = ArrayBuffer[String](), runFlags: ArrayBuffer[String] = ArrayBuffer[String](), usePluginsCache: Boolean = true, pluginsCachePath: String = "./simWorkspace/.pluginsCachePath", enableLogging: Boolean = false, timePrecision: TimeNumber = null, simSetupFile: String = null, envSetup: () ⇒ Unit = null, vcsFlags: VCSFlags = null, compileFlags: ArrayBuffer[String] = ArrayBuffer[String](), elaborateFlags: ArrayBuffer[String] = ArrayBuffer[String](), vcsCC: Option[String] = None, vcsLd: Option[String] = None, testPath: String = null) extends SpinalVpiBackendConfig[T] with Product with Serializable
- case class SpinalVerilatorBackendConfig[T <: Component](rtl: SpinalReport[T], waveFormat: WaveFormat = WaveFormat.NONE, maxCacheEntries: Int = 100, cachePath: String = null, workspacePath: String = "./", workspaceName: String = null, vcdPath: String = null, vcdPrefix: String = null, waveDepth: Int = 0, optimisationLevel: Int = 2, simulatorFlags: ArrayBuffer[String] = ArrayBuffer[String](), withCoverage: Boolean, timePrecision: TimeNumber = null, testPath: String) extends Product with Serializable
- class SpinalVpiBackendConfig[T <: Component] extends AnyRef
- case class SpinalXSimBackendConfig[T <: Component](rtl: SpinalReport[T], xciSourcesPaths: ArrayBuffer[String] = ArrayBuffer[String](), bdSourcesPaths: ArrayBuffer[String] = ArrayBuffer[String](), waveFormat: WaveFormat, workspacePath: String, workspaceName: String, wavePath: String, xilinxDevice: String, simScript: String, simulatorFlags: ArrayBuffer[String] = ArrayBuffer[String](), timePrecision: TimeNumber = null) extends Product with Serializable
-
class
SwapTagPhase extends PhaseNetlist
Swap all oldTag with newTag
Value Members
- def SimConfig: SpinalSimConfig
- def addInputsAssignmentWatch(mod: Module): Unit
- def addWatchedSignals(signals: Seq[BaseType]): Unit
- def checkInputsAssignmentAfterReset(cd: ClockDomain, stopOnFail: Boolean = false): Unit
- def checkWatchedSignalAssigned(): Seq[String]
- def currentTestName(): String
- def currentTestPath(): String
- def delayed(delay: TimeNumber)(body: ⇒ Unit): Unit
- def delayed(delay: Long)(body: ⇒ Unit): Unit
- def disableSimWave(): Unit
- def enableSimWave(): Unit
-
def
fork(body: ⇒ Unit): SimThread
Fork
- def forkJoin(bodys: () ⇒ Unit*): Unit
- def forkSensitive(trigger: ⇒ Any)(block: ⇒ Unit): Unit
- def forkSensitive(triggers: Data)(block: ⇒ Unit): Unit
- def forkSensitive(block: ⇒ Unit): Unit
- def forkSensitive2(triggers: Data*)(block: ⇒ Unit): Unit
- def forkSensitiveWhile(block: ⇒ Boolean): Unit
- def forkSimSporadicWave(captures: Seq[(Double, Double)], enableTime: Double = 1e-7, disableTime: Double = 1e-4, timeUnit: Double = 1e12): Unit
- def getBigInt[T <: Data](mem: Mem[T], address: Long): BigInt
- def getForbiddenRandom(): AtomicLong
- def hzToLong(hz: HertzNumber): Long
- def killRandom(): Unit
- def onSimEnd(body: ⇒ Unit): Unit
- def periodicaly(delay: Long)(body: ⇒ Unit): Unit
-
def
setBigInt(bt: BaseType, value: BigInt): Unit
Set a BigInt value to a BaseType
- def setBigInt[T <: Data](mem: Mem[T], address: Long, data: BigInt): Unit
-
def
setLong(bt: BaseType, value: Long): Unit
Set a long value to a BaseType
- def simCompiled: SimCompiled[_ <: Component]
- def simDeltaCycle(): Long
- def simFailure(message: String = ""): Nothing
- def simRandom(implicit simManager: SimManager = sm): Random
-
def
simSuccess(): Nothing
Success/Failure simulation
- def simThread: SimThread
-
def
simTime(): Long
Return the current simulation time
- def sleep(time: TimeNumber): Unit
- def sleep(cycles: Double): Unit
-
def
sleep(cycles: Long): Unit
Sleep / WaitUntil
- def sm: SimManager
- def timePrecision: BigDecimal
- def timeToLong(time: TimeNumber): Long
- def waitUntil(cond: ⇒ Boolean): Unit
-
object
DoClock
Generate a clock
-
object
DoReset
Execute a reset sequence
-
object
ForkClock
Fork the DoClock
-
object
SimPublic extends SpinalTag
Tag SimPublic
-
object
SimSpeedPrinter
Print the simulation speed
- object SimStatics
-
object
SimTimeout
Create a Timeout for the simulation
- object SimUnionElementPimper
-
object
SimWorkspace
Simulation Workspace
- object SpinalGhdlBackend
- object SpinalIVerilogBackend
- object SpinalSimBackendSel
- object SpinalVCSBackend
- object SpinalVerilatorBackend
- object SpinalVerilatorSim
- object SpinalVpiBackend
- object SpinalXSimBackend
- object TracingOff extends SpinalTag
Deprecated Value Members
-
def
SimConfig[T <: Component](rtl: SpinalReport[T]): SimConfigLegacy[T]
- Annotations
- @deprecated
- Deprecated
(Since version ???) Use SimConfig.???.compile(new Dut) instead
-
def
SimConfig[T <: Component](rtl: ⇒ T): SimConfigLegacy[T]
- Annotations
- @deprecated
- Deprecated
(Since version ???) Use SimConfig.???.compile(new Dut) instead