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package core

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  1. core
  2. BaseTypeCast
  3. UFixCast
  4. SFixCast
  5. BaseTypeFactory
  6. UFixFactory
  7. SFixFactory
  8. TypeFactory
  9. VecFactory
  10. SIntFactory
  11. UIntFactory
  12. BitsFactory
  13. BoolFactory
  14. AnyRef
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Type Members

  1. class AFix extends MultiData with Num[AFix] with BitwiseOp[AFix] with MinMaxDecimalProvider
  2. trait AllowIoBundle extends AnyRef
  3. trait Area extends NameableByComponent with ContextUser with OwnableRef with ScalaLocated with ValCallbackRec with OverridedEqualsHashCode

    Sometime, creating a Component to define some logic is overkill.

    Sometime, creating a Component to define some logic is overkill. For this kind of cases you can use Area to define a group of signals/logic.

    Example: 

    1. val tickConter = new Area{
  val tick = Reg(UInt(8 bits) init(0)
  tick := tick + 1
}
    See also

    Area Documentation

  4. trait AreaObject extends Area
  5. trait AreaRoot extends Area
  6. trait AssertNodeSeverity extends AnyRef
  7. trait Assignable extends AnyRef

    Assignable trait

  8. trait Attribute extends SpinalTag
  9. class AttributeFlag extends Attribute
  10. class AttributeInteger extends Attribute
  11. sealed trait AttributeKind extends AnyRef
  12. class AttributeString extends Attribute
  13. abstract class BaseType extends Data with DeclarationStatement with StatementDoubleLinkedContainer[BaseType, AssignmentStatement] with Expression

    Abstract base class of all Spinal types

  14. trait BaseTypeCast extends SFixCast with UFixCast

    Base type Cast

  15. trait BaseTypeFactory extends BoolFactory with BitsFactory with UIntFactory with SIntFactory with VecFactory with SFixFactory with UFixFactory

    Base type factory

  16. class BaseTypePimper[T <: BaseType] extends AnyRef
  17. trait BaseTypePrimitives[T <: BaseType] extends AnyRef
  18. implicit class BigDecimalBuilder extends AnyRef

    BigDecimal Builder

  19. case class BigIntBuilder(i: BigInt) extends Product with Serializable

    BigInt Builder

  20. case class BitCount(value: Int) extends Product with Serializable

    Represent the number of bit of a data

  21. abstract class BitVector extends BaseType with Widthable

    BitVector is a family of types for storing multiple bits of information in a single value.

    BitVector is a family of types for storing multiple bits of information in a single value. This type has three subtypes that can be used to model different behaviors:

    • Bits
    • UInt (unsigned integer)
    • SInt (signed integer)
    See also

    BitVector family Documentation

  22. abstract class BitVectorLiteralFactory[T <: BitVector] extends AnyRef

    Base class to create Bit Vector from literal

  23. class Bits extends BitVector with DataPrimitives[Bits] with BaseTypePrimitives[Bits] with BitwiseOp[Bits]

    The Bits type corresponds to a vector of bits that does not convey any arithmetic meaning.

    The Bits type corresponds to a vector of bits that does not convey any arithmetic meaning.

    Example: 

    1. val myBits1 = Bits(32 bits)
val myBits2 = B(25, 8 bits)
val myBits3 = B"8'xFF"
val myBits4 = B"1001_0011
    See also

    Bits Documentation

  24. trait BitsFactory extends AnyRef

    Bits factory used for instance by the IODirection to create a in/out Bits

  25. trait BitwiseOp[T <: Data] extends AnyRef

    Bitwise Operation

    Bitwise Operation

    T

    the type which is associated with the bitwise operation

  26. abstract class BlackBox extends Component

    A blackbox allows the user to integrate an existing VHDL/Verilog component into the design by just specifying the interfaces.

    A blackbox allows the user to integrate an existing VHDL/Verilog component into the design by just specifying the interfaces.

    Example: 

    1.  class Ram_1w_1r(wordWidth: Int, wordCount: Int) extends BlackBox {
     val generic = new Generic {
         val wordCount = Ram_1w_1r.this.wordCount
         val wordWidth = Ram_1w_1r.this.wordWidth
     }
     val io = new Bundle {
         val clk = in Bool()
         val wr = new Bundle {
             val en   = in Bool()
             val addr = in UInt (log2Up(wordCount) bit)
             val data = in Bits (wordWidth bit)
         }
         val rd = new Bundle {
             val en   = in Bool()
             val addr = in UInt (log2Up(wordCount) bit)
             val data = out Bits (wordWidth bit)
         }
     }
     mapClockDomain(clock=io.clk)
}
  27. class BlackBoxImpl extends AnyRef
  28. abstract class BlackBoxULogic extends BlackBox

    Create a blackBox with std_ulogic instead of std_logic

  29. class Bool extends BaseType with DataPrimitives[Bool] with BaseTypePrimitives[Bool] with BitwiseOp[Bool]

    The Bool type corresponds to a hardware boolean value (True or False)

    The Bool type corresponds to a hardware boolean value (True or False)

    Example: 

    1. val myBool = Bool()
myBool := False
myBool := Bool(false)
    See also

    Bool Documentation

  30. case class BoolEdges() extends Bundle with Product with Serializable

    Bundle for the edge detection

  31. trait BoolFactory extends AnyRef

    Bool factory used for instance by the IODirection to create a in/out Bool()

  32. class Bundle extends MultiData with Nameable with ValCallbackRec

    A Bundle is a composite type that defines a group of named signals (of any SpinalHDL basic type) under a single name.

    A Bundle is a composite type that defines a group of named signals (of any SpinalHDL basic type) under a single name. A Bundle can be used to model data structures, buses and interfaces.

    Example: 

    1. val cmd = new Bundle{
  val init   = in Bool()
  val start  = in Bool()
  val result = out Bits(32 bits)
}
    See also

    Bundle Documentation

  33. class BundleCase extends Bundle
  34. case class ClockDomain(clock: Bool, reset: Bool = null, dummyArg: DummyTrait = null, softReset: Bool = null, clockEnable: Bool = null, config: ClockDomainConfig = GlobalData.get.commonClockConfig, frequency: ClockFrequency = UnknownFrequency(), clockEnableDivisionRate: DivisionRate = ClockDomain.UnknownDivisionRate()) extends SpinalTagReady with Product with Serializable

    Represents the combined clock and reset signals for an hardware domain.

    Represents the combined clock and reset signals for an hardware domain.

    Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain. Clock domain application work like a stack, which mean, if you are in a given clock domain, you can still apply another clock domain locally.

    clock

    Clock signal that defines the domain

    reset

    Reset signal. If a register exists which needs a reset and the clock domain doesn’t provide one, an error message will be displayed.

    softReset

    Reset which infers an additional synchronous reset

    clockEnable

    Disable the clock on the whole clock domain without having to manually implement that on each synchronous element.

    config

    Specify the polarity of signals and the nature of the reset.

    frequency

    Allows you to specify the frequency of the given clock domain and later read it in your design. This parameter does not generate a PLL or more hardware to control the frequency.

    See also

    clock domains documentation

  35. sealed trait ClockDomainBoolTag extends SpinalTag
  36. case class ClockDomainConfig(clockEdge: EdgeKind = RISING, resetKind: ResetKind = ASYNC, resetActiveLevel: Polarity = HIGH, softResetActiveLevel: Polarity = HIGH, clockEnableActiveLevel: Polarity = HIGH) extends Product with Serializable

    The caracteristic (rising, async, high, e.g.) of the control signals of a ClockDomain

    The caracteristic (rising, async, high, e.g.) of the control signals of a ClockDomain

    clockEdge

    can be RISING (default) or FALLING

    resetKind

    can be ASYNC (default), SYNC or BOOT which is supported by some FPGAs (where FF values are loaded by the bitstream)

    resetActiveLevel

    can be HIGH (default), or LOW

    softResetActiveLevel

    can be HIGH (default), or LOW

    clockEnableActiveLevel

    can be HIGH (default), or LOW

    See also

    Clock domain documentation

  37. case class ClockDomainReportTag(clockDomain: ClockDomain) extends SpinalTag with Product with Serializable
  38. case class ClockDomainTag(clockDomain: ClockDomain) extends SpinalTag with Product with Serializable
  39. case class ClockDrivedTag(driver: Bool) extends SpinalTag with Product with Serializable
  40. case class ClockDriverTag(drived: Bool) extends SpinalTag with Product with Serializable
  41. class ClockEnableArea extends Area with PostInitCallback

    Clock Area with a special clock enable.

    Clock Area with a special clock enable.

    See also

    ClockEnableArea documentation

  42. case class ClockEnableTag(clockDomain: ClockDomain) extends ClockDomainBoolTag with Product with Serializable
  43. case class ClockSyncTag(a: Bool, b: Bool) extends SpinalTag with Product with Serializable
  44. case class ClockTag(clockDomain: ClockDomain) extends ClockDomainBoolTag with Product with Serializable
  45. class ClockingArea extends Area with PostInitCallback

    Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain.

    Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain.

    See also

    Clock domains documentation

  46. class CommentTag extends SpinalTag
  47. abstract class Component extends NameableByComponent with ContextUser with ScalaLocated with PostInitCallback with Stackable with OwnableRef with SpinalTagReady with OverridedEqualsHashCode with ValCallbackRec

    Abstract class used to create a new Component

    Abstract class used to create a new Component

    Example: 

    1. class MyAndGate extends Component {
  val io = new Bundle{
    val a,b = in Bool()
    val res = out Bool()
  }
  io.res := io.a & io.b
}
    See also

    Component Documentation

  48. class Composite[T <: Nameable] extends Area
  49. trait ConditionalContext extends GlobalDataUser
  50. trait ContextUser extends GlobalDataUser with ScalaLocated
  51. class CrossClockBufferDepth extends SpinalTag
  52. case class CyclesCount(value: BigInt) extends Product with Serializable

    Cycles number representation

  53. trait Data extends ContextUser with NameableByComponent with Assignable with SpinalTagReady with GlobalDataUser with ScalaLocated with OwnableRef with OverridedEqualsHashCode with InComponent
  54. class DataPimper[T <: Data] extends DataPrimitives[T]

    Should not extends AnyVal, Because it create kind of strange call stack move that make error reporting miss accurate

  55. trait DataPrimitives[T <: Data] extends AnyRef
  56. implicit class DataSimInitPimper[T <: Data] extends AnyRef

    Extension methods for register simulation initialization

  57. trait DataWrapper extends Data
  58. class DefaultTag extends SpinalTag
  59. case class Device(vendor: String = "?", family: String = "?", name: String = "?", supportBootResetKind: Boolean = true) extends Product with Serializable

    target device

  60. class DontName extends Annotation with Annotation with ClassfileAnnotation
    Annotations
    @Retention()
  61. case class DoubleBuilder(d: Double) extends Product with Serializable

    Double Builder

  62. trait DummyTrait extends AnyRef
  63. case class DumpWaveConfig(depth: Int = 0, vcdPath: String = "wave.vcd") extends Product with Serializable
  64. trait DuringWritePolicy extends AnyRef
  65. sealed trait EdgeKind extends AreaObject
  66. class ElseWhenClause extends AnyRef
  67. implicit class ElseWhenClauseBuilder extends AnyRef

    Implicit clause builder for elseWhen

  68. sealed trait Endianness extends AnyRef

    Endianness enumeration

  69. class EnumLiteral[T <: SpinalEnum] extends Literal with InferableEnumEncodingImpl

    Node representation which contains the value of an SpinalEnumElement

  70. class EnumPoison extends Literal with InferableEnumEncodingImpl
  71. case class ExpNumber(value: Int) extends Product with Serializable

    Exponent representation

  72. class ExternalDriverTag extends SpinalTag
  73. case class FixPointConfig(roundType: RoundType, symmetric: Boolean) extends Product with Serializable
  74. type FixedFrequency = core.ClockDomain.FixedFrequency
  75. class GenerationFlags extends AnyRef
  76. class Generic extends AnyRef

    Create a generic for a BlackBox

    Create a generic for a BlackBox

    Example: 

    1. class myMemory(sizeMem: Int) extends BlackBox{
    val generic = new Generic{
     val size = sizeMem
    }
    val io = new Bundle { ... }
}
  77. case class GenericValue(e: Expression) extends SpinalTag with Product with Serializable
  78. class GlobalData extends AnyRef

    Global data

  79. trait GlobalDataUser extends AnyRef

    Get a link to the globalData

  80. class HardMap extends MultiData
  81. class HardType[T <: Data] extends OverridedEqualsHashCode
  82. case class HertzNumber(v: BigDecimal) extends PhysicalNumber[HertzNumber] with Product with Serializable

    Frequency representation

  83. type IClockDomainFrequency = ClockFrequency
  84. trait IConnectable[T <: IConnectable[T]] extends AnyRef
  85. sealed trait IODirection extends BaseTypeFactory

    Declare ports

    Declare ports

    A port is some Data with a direction, which can be in, out or inout.

    There are 4 available syntaxes, which are all equivalent:

    val braces = in(Vec(Bool, 5))

val short = in Vec (Bool, 5)

val spaceful = in port Vec(Bool, 5)

val variadic = Vec(Bool, 5)
in(variadic)

    The "braces" syntax is short and generic, but it uses braces.

    The "short" syntax is short, but it is formatted with a space between the type and its parameters, and it can be used only with:

    The "spaceful" syntax is generic and beautiful, but more verbose.

    The "variadic" syntax can be used with any number of ports, but can be used only if the ports types are already declared.

    See also

    in out inout

  86. class IfDefTag extends SpinalTag
  87. abstract class ImplicitArea[T] extends Area

    Create an Area which can be assign to a data

    Create an Area which can be assign to a data

    Example: 

    1. class Counter extends ImplicitArea[UInt]{
   val cnt = Reg(UInt(8 bits)
   ...
   override def implicitValue: UInt = cnt
}
val myCounter = Counter()
io.myUInt = myCounter
  88. trait InComponent extends AnyRef
  89. final class IntBuilder extends AnyVal

    Integer Builder

  90. class Interface extends Bundle

    system verilog interface

    system verilog interface

    Example

    case class MyIf(width: Int = 8) extends Interface with IMasterSlave {
 val wParam = addGeneric("WIDTH", width, default = "8")
 val a = Bits(width bits)
 tieGeneric(a, wParam)
 val b = Bool()
 val c = SInt(8 bits)

 override def asMaster = mst
 @modport
 def mst = {
   out(a, b, c)
 }

 @modport
 def slv = {
   in(a, b, c)
 }

}
  91. sealed trait Language extends AnyRef
  92. implicit class LiteralBuilder extends AnyRef

    Literal builder

    Literal builder 

    S/U/B"[[size']base]value"

    e.g.: 

    B"8'xFF"`
  93. class MaskedBoolean extends AnyRef

    Masked Literal

    Masked Literal

    Example: 

    1. val itMatch = myBits === M"00--10--" // - don't care value
  94. class MaskedLiteral extends AnyRef
  95. class Mem[T <: Data] extends DeclarationStatement with StatementDoubleLinkedContainer[Mem[_], MemPortStatement] with WidthProvider with SpinalTagReady with InComponent

    An hardware memory.

    An hardware memory.

    See also

    RAM/ROM Memory documentation

  96. trait MemBlackboxingPolicy extends AnyRef

    Policy for memory blackbox replacement.

    Policy for memory blackbox replacement.

    See also

    RAM/ROM Blackboxing policy documentation

  97. trait MemPortStatement extends LeafStatement with StatementDoubleLinkedContainerElement[Mem[_], MemPortStatement] with Nameable with SpinalTagReady
  98. class MemReadAsync extends MemPortStatement with WidthProvider with ContextUser with Expression
  99. class MemReadSync extends MemPortStatement with WidthProvider with ContextUser with Expression
  100. class MemReadWrite extends MemPortStatement with WidthProvider with ContextUser with Expression
  101. case class MemSymbolesMapping(name: String, range: Range) extends Product with Serializable
  102. case class MemSymbolesTag(mapping: Seq[MemSymbolesMapping]) extends SpinalTag with Product with Serializable
  103. trait MemTechnologyKind extends AnyRef
  104. class MemWrite extends MemPortStatement with WidthProvider
  105. class MemWritePayload[T <: Data] extends Bundle
  106. trait MinMaxDecimalProvider extends AnyRef
  107. trait MinMaxProvider extends AnyRef

    Min max base function

  108. type Module = Component
  109. abstract class MultiData extends Data

    Base class for multi data like Vec, Bundle

  110. trait Nameable extends OwnableRef with ContextUser
  111. trait NameableByComponent extends Nameable with GlobalDataUser
  112. class NamedType[T <: Data] extends HardType[T] with Nameable
  113. class NamingScope extends AnyRef
  114. trait Num[T <: Data] extends AnyRef

    Base operations for numbers

    Base operations for numbers

    T

    the type which is associated with the base operation

  115. case class ObfuscateConfig(keepDefinitionNames: Boolean = false, keepInstanceNames: Boolean = false, keepClkResetNames: Boolean = false, prefix: String = "oo_", hierarchyKeepLevel: Int = 0) extends Product with Serializable
  116. trait OverridedEqualsHashCode extends AnyRef
  117. trait OwnableRef extends AnyRef
  118. abstract class PhysicalNumber[T <: PhysicalNumber[_]] extends Formattable

    Base class for the Physical representation (Hertz, Time, ...)

    Base class for the Physical representation (Hertz, Time, ...)

    When formatting (e.g. via f-interpolation) one can use: - precision to specify precsion (e.g. "%.3f" for three digits past comma) - width to pad with space to a specified length (e.g. "%5f" to get at least 5 characters) - left justified padding (e.g. "%-5f" to pad right to 5 characters) - alternate to print w/o unit (e.g. "%#f")

  119. implicit final class PhysicalNumberPimper extends AnyVal
  120. sealed trait Polarity extends AreaObject
  121. case class PosCount(value: Int) extends Product with Serializable

    Position representation

  122. case class QFormat(width: Int, fraction: Int, signed: Boolean) extends Product with Serializable
  123. class Ram_1w_1ra extends BlackBox
  124. class Ram_1w_1rs extends BlackBox
  125. class Ram_1wors extends BlackBox
  126. class Ram_1wrs extends BlackBox
  127. class Ram_2c_1w_1rs extends BlackBox
  128. class Ram_2wrs extends BlackBox
  129. class Ram_Generic extends BlackBox
  130. implicit class RangePimper extends AnyRef

    Implicit Range helper

  131. trait ReadUnderWritePolicy extends AnyRef

    Policy of a Mem when read under write.

    Policy of a Mem when read under write.

    See also

    RAM/ROM documentation

  132. case class Ref[T](value: T) extends Product with Serializable

    Use to give value by reference to a function

  133. class ResetArea extends Area with PostInitCallback

    ResetArea allow to reset an area with a special reset combining with the current reset (cumulative).

    ResetArea allow to reset an area with a special reset combining with the current reset (cumulative).

    See also

    ResetArea documentation

  134. sealed trait ResetKind extends AreaObject
  135. case class ResetTag(clockDomain: ClockDomain) extends ClockDomainBoolTag with Product with Serializable
  136. sealed trait RoundType extends AnyRef
  137. class SFix extends XFix[SFix, SInt]

    Signed fix point

    Signed fix point

    See also

    UFix/SFix Documentation

  138. class SFix2D extends Bundle
  139. trait SFixCast extends AnyRef
  140. trait SFixFactory extends TypeFactory
  141. class SInt extends BitVector with Num[SInt] with MinMaxProvider with DataPrimitives[SInt] with BaseTypePrimitives[SInt] with BitwiseOp[SInt]

    The SInt type corresponds to a vector of bits that can be used for signed integer arithmetic.

    The SInt type corresponds to a vector of bits that can be used for signed integer arithmetic.

    Example: 

    1. val mySInt = SInt(8 bits)
mySInt    := S(4, 8 bits) + S"0000_1111"
mySInt    := S(4) - S"h1A"
    See also

    UInt/SInt Documentation]]

  142. trait SIntFactory extends AnyRef

    SInt factory used for instance by the IODirection to create a in/out SInt

  143. implicit class SIntPimper extends AnyRef

    Implicit SInt helper

  144. class SafeStack[T] extends AnyRef

    Safe Stack

  145. class SafeStackWithStackable[T <: Stackable] extends SafeStack[T]
  146. trait ScalaLocated extends GlobalDataUser
  147. class ScopeProperty[T] extends AnyRef
  148. class ScopePropertyContext extends AnyRef
  149. class ScopePropertyValue extends AnyRef
  150. case class SimInitTag(value: Expression) extends SpinalTag with Product with Serializable

    SimInit tag for register simulation initialization Sets simulation-only initial values via Verilog initial blocks

  151. case class SlicesCount(value: Int) extends Product with Serializable

    Slice size representation

  152. class SlowArea extends ClockingArea

    Define a clock domain which is x time slower than the current clock.

    Define a clock domain which is x time slower than the current clock.

    See also

    SlowArea documentation

  153. case class SpinalConfig(mode: SpinalMode = null, flags: HashSet[Any] = mutable.HashSet[Any](), debugComponents: HashSet[Class[_]] = mutable.HashSet[Class[_]](), keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = SpinalConfig.defaultTargetDirectory, oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", privateNamespace: Boolean = false, formalAsserts: Boolean = false, anonymSignalPrefix: String = null, device: Device = Device(), inlineRom: Boolean = false, caseRom: Boolean = false, romReuse: Boolean = false, genVhdlPkg: Boolean = true, verbose: Boolean = false, mergeAsyncProcess: Boolean = false, mergeSyncProcess: Boolean = true, asyncResetCombSensitivity: Boolean = false, anonymSignalUniqueness: Boolean = false, inlineConditionalExpression: Boolean = false, nameWhenByFile: Boolean = true, genLineComments: Boolean = false, noRandBoot: Boolean = false, randBootFixValue: Boolean = true, noAssert: Boolean = false, fixToWithWrap: Boolean = true, headerWithDate: Boolean = false, headerWithRepoHash: Boolean = true, removePruned: Boolean = false, allowOutOfRangeLiterals: Boolean = false, dontCareGenAsZero: Boolean = false, obfuscateNames: Boolean = false, obfuscate: ObfuscateConfig = ObfuscateConfig(), normalizeComponentClockDomainName: Boolean = false, devicePhaseHandler: PhaseDeviceHandler = PhaseDeviceDefault, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit] = ..., transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ..., rtlHeader: String = null, scopeProperties: LinkedHashMap[ScopeProperty[_], Any] = ..., _withEnumString: Boolean = true, enumPrefixEnable: Boolean = true, enumGlobalEnable: Boolean = false, bitVectorWidthMax: Int = 4096, singleTopLevel: Boolean = true, noAssertAtTimeZero: Boolean = false, cutLongExpressions: Boolean = true, withTimescale: Boolean = true, printFilelist: Boolean = true, emitFullComponentBindings: Boolean = true, reportIncludeSourceLocation: Boolean = false, reportSourceLocationFormat: String = ..., svInterface: Boolean = false) extends Product with Serializable

    Spinal configuration for the generation of the RTL

    Spinal configuration for the generation of the RTL

    See also

    VHDL and Verilog generation doc

  154. class SpinalEnum extends Nameable with ScalaLocated

    Base class for creating enumeration

    Base class for creating enumeration

    Example: 

    1. object MyEnum extends SpinalEnum(binarySequential){
  val s1, s2, s3, s4 = newElement()
}

      SpinalEnum contains a list of SpinalEnumElement that is the definition of an element. SpinalEnumCraft is the hardware representation of the the element.

    See also

    Enumeration Documentation

  155. class SpinalEnumCraft[T <: SpinalEnum] extends BaseType with InferableEnumEncodingImpl with BaseTypePrimitives[SpinalEnumCraft[T]] with DataPrimitives[SpinalEnumCraft[T]]

    Hardware representation of an enumeration

  156. class SpinalEnumElement[T <: SpinalEnum] extends Nameable with SpinalTagReady

    Definition of an element of the enumeration

  157. trait SpinalEnumEncoding extends Nameable with ScalaLocated

    Trait to define an encoding

  158. class SpinalExit extends Exception
  159. trait SpinalMode extends AnyRef
  160. class SpinalReport[T <: Component] extends AnyRef

    Spinal report give after the generation of the RTL

  161. abstract class SpinalStruct extends BaseType with Nameable with ValCallbackRec with DataPrimitives[SpinalStruct] with Suffixable

    Class representing Verilog Struct and VHDL Record data types.

  162. trait SpinalTag extends AnyRef
  163. trait SpinalTagGetter[T] extends SpinalTag
  164. trait SpinalTagReady extends AnyRef
  165. trait Stackable extends AnyRef
  166. class SwitchContext extends AnyRef
  167. class TagAFixTruncated extends SpinalTag
  168. case class TimeNumber(v: BigDecimal) extends PhysicalNumber[TimeNumber] with Product with Serializable

    Time representation

  169. sealed trait TimingEndpointType extends AnyRef
  170. class ToBitsPimper extends AnyRef
  171. implicit class Tuple10Pimper extends TuplePimperBase
  172. implicit class Tuple11Pimper extends TuplePimperBase
  173. implicit class Tuple12Pimper extends TuplePimperBase
  174. implicit class Tuple13Pimper extends TuplePimperBase
  175. implicit class Tuple14Pimper extends TuplePimperBase
  176. implicit class Tuple15Pimper extends TuplePimperBase
  177. implicit class Tuple16Pimper extends TuplePimperBase
  178. implicit class Tuple17Pimper extends TuplePimperBase
  179. implicit class Tuple18Pimper extends TuplePimperBase
  180. implicit class Tuple19Pimper extends TuplePimperBase
  181. implicit class Tuple20Pimper extends TuplePimperBase
  182. implicit class Tuple21Pimper extends TuplePimperBase
  183. implicit class Tuple22Pimper extends TuplePimperBase
  184. implicit class Tuple2Pimper extends TuplePimperBase
  185. implicit class Tuple3Pimper extends TuplePimperBase
  186. implicit class Tuple4Pimper extends TuplePimperBase
  187. implicit class Tuple5Pimper extends TuplePimperBase
  188. implicit class Tuple6Pimper extends TuplePimperBase
  189. implicit class Tuple7Pimper extends TuplePimperBase
  190. implicit class Tuple8Pimper extends TuplePimperBase
  191. implicit class Tuple9Pimper extends TuplePimperBase
  192. case class TupleBundle1[T1 <: Data](payloadType1: HardType[T1]) extends TupleBundleBase with Product with Serializable
  193. case class TupleBundle10[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10]) extends TupleBundleBase with Product with Serializable
  194. case class TupleBundle11[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11]) extends TupleBundleBase with Product with Serializable
  195. case class TupleBundle12[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12]) extends TupleBundleBase with Product with Serializable
  196. case class TupleBundle13[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13]) extends TupleBundleBase with Product with Serializable
  197. case class TupleBundle14[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14]) extends TupleBundleBase with Product with Serializable
  198. case class TupleBundle15[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15]) extends TupleBundleBase with Product with Serializable
  199. case class TupleBundle16[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16]) extends TupleBundleBase with Product with Serializable
  200. case class TupleBundle17[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17]) extends TupleBundleBase with Product with Serializable
  201. case class TupleBundle18[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17], payloadType18: HardType[T18]) extends TupleBundleBase with Product with Serializable
  202. case class TupleBundle19[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17], payloadType18: HardType[T18], payloadType19: HardType[T19]) extends TupleBundleBase with Product with Serializable
  203. case class TupleBundle2[T1 <: Data, T2 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2]) extends TupleBundleBase with Product with Serializable
  204. case class TupleBundle20[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17], payloadType18: HardType[T18], payloadType19: HardType[T19], payloadType20: HardType[T20]) extends TupleBundleBase with Product with Serializable
  205. case class TupleBundle21[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data, T21 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17], payloadType18: HardType[T18], payloadType19: HardType[T19], payloadType20: HardType[T20], payloadType21: HardType[T21]) extends TupleBundleBase with Product with Serializable
  206. case class TupleBundle22[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data, T21 <: Data, T22 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9], payloadType10: HardType[T10], payloadType11: HardType[T11], payloadType12: HardType[T12], payloadType13: HardType[T13], payloadType14: HardType[T14], payloadType15: HardType[T15], payloadType16: HardType[T16], payloadType17: HardType[T17], payloadType18: HardType[T18], payloadType19: HardType[T19], payloadType20: HardType[T20], payloadType21: HardType[T21], payloadType22: HardType[T22]) extends TupleBundleBase with Product with Serializable
  207. case class TupleBundle3[T1 <: Data, T2 <: Data, T3 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3]) extends TupleBundleBase with Product with Serializable
  208. case class TupleBundle4[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4]) extends TupleBundleBase with Product with Serializable
  209. case class TupleBundle5[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5]) extends TupleBundleBase with Product with Serializable
  210. case class TupleBundle6[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6]) extends TupleBundleBase with Product with Serializable
  211. case class TupleBundle7[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7]) extends TupleBundleBase with Product with Serializable
  212. case class TupleBundle8[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8]) extends TupleBundleBase with Product with Serializable
  213. case class TupleBundle9[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data](payloadType1: HardType[T1], payloadType2: HardType[T2], payloadType3: HardType[T3], payloadType4: HardType[T4], payloadType5: HardType[T5], payloadType6: HardType[T6], payloadType7: HardType[T7], payloadType8: HardType[T8], payloadType9: HardType[T9]) extends TupleBundleBase with Product with Serializable
  214. class TupleBundleBase extends Bundle
  215. class TuplePimperBase extends AnyRef
  216. trait TypeFactory extends AnyRef
  217. class UFix extends XFix[UFix, UInt]

    Unsigned fix point

    Unsigned fix point

    See also

    UFix/SFix Documentation

  218. class UFix2D extends Bundle

    Two-dimensional XFix

  219. trait UFixCast extends AnyRef
  220. trait UFixFactory extends TypeFactory
  221. class UInt extends BitVector with Num[UInt] with MinMaxProvider with DataPrimitives[UInt] with BaseTypePrimitives[UInt] with BitwiseOp[UInt]

    The hardware UInt type corresponds to a vector of bits usable for unsigned integer arithmetic.

    The hardware UInt type corresponds to a vector of bits usable for unsigned integer arithmetic.

    Example: 

    1. val myUInt = UInt(8 bits)
 myUInt := U(2,8 bits)
 myUInt := U(2)
 myUInt := U"0000_0101"
 myUInt := U"h1A"
    See also

    UInt/SInt Documentation

  222. case class UInt2D(xBitCount: BitCount, yBitCount: BitCount) extends Bundle with Product with Serializable

    Define an UInt 2D point

    Define an UInt 2D point

    xBitCount

    width of the x point

    yBitCount

    width of the y point

    Example: 

    1. val positionOnScreen = Reg(UInt2D(log2Up(p.screenResX) bits, log2Up(p.screenResY) bits))
  223. trait UIntFactory extends AnyRef

    UInt factory used for instance by the IODirection to create a in/out UInt

  224. implicit class UIntPimper extends AnyRef

    Implicit UInt helper

  225. class Union extends MultiData with PostInitCallback
  226. class UnionElement[T <: Data] extends AnyRef
  227. type UnknownFrequency = core.ClockDomain.UnknownFrequency
  228. trait ValCallbackRec extends ValCallback
  229. class VarAssignementTag extends SpinalTag
  230. class Vec[T <: Data] extends MultiData with IndexedSeq[T]

    A Vec is a composite type that defines a group of indexed signals (of any SpinalHDL basic type) under a single name

    A Vec is a composite type that defines a group of indexed signals (of any SpinalHDL basic type) under a single name

    Example: 

    1. val myVecOfSInt = Vec(SInt(8 bits), 2)
    See also

    Vec Documentation

  231. class VecAccessAssign[T <: Data] extends Assignable
  232. class VecBitwisePimper[T <: Data with BitwiseOp[T]] extends BitwiseOp[Vec[T]]
  233. trait VecFactory extends AnyRef

    Vec factory

  234. class VecBuilder extends AnyRef
    Definition Classes
    VecFactory
  235. case class VerilogValues(v: String) extends Product with Serializable
  236. class WhenContext extends ConditionalContext with ScalaLocated

    Used by SpinalHDL when/elsewhen/otherwise and WhenBuilder to keep track of the structure.

  237. abstract class XFix[T <: XFix[T, R], R <: BitVector with Num[R]] extends MultiData with MinMaxDecimalProvider

    Base class for SFix and UFix

  238. case class crossClockFalsePath(source: Option[BaseType] = None, destType: TimingEndpointType = TimingEndpointType.DATA) extends SpinalTag with Product with Serializable
  239. case class crossClockMaxDelay(cycles: Int, useTargetClock: Boolean) extends SpinalTag with Product with Serializable
  240. type dontName = spinal.core.DontName @scala.annotation.meta.field
  241. class modport extends Annotation with Annotation with ClassfileAnnotation
    Annotations
    @Retention()
  242. case class reportSourceLocationFormatTag(format: String) extends SpinalTag with Product with Serializable

Value Members

  1. implicit def BaseTypePimped[T <: BaseType](that: T): BaseTypePimper[T]
  2. implicit def BigIntToBits(that: BigInt): Bits
  3. implicit def BigIntToBuilder(value: BigInt): BigIntBuilder
  4. implicit def BigIntToSInt(that: BigInt): SInt
  5. implicit def BigIntToUInt(that: BigInt): UInt
  6. def Bits(width: BitCount): Bits

    Create a new Bits of a given width

    Create a new Bits of a given width

    Definition Classes
    BitsFactory
  7. def Bits(u: Unit = ()): Bits

    Create a new Bits

    Create a new Bits

    Definition Classes
    BitsFactory
  8. def Bool(value: Boolean)(implicit loc: Location): Bool

    Create a new Bool with a value

    Create a new Bool with a value

    Definition Classes
    BoolFactory
  9. def Bool(u: Unit = ()): Bool

    Create a new Bool

    Create a new Bool

    Definition Classes
    BoolFactory
  10. implicit def BooleanPimped(that: Boolean): BooleanPimped
  11. implicit def DataPimped[T <: Data](that: T): DataPimper[T]

    Implicit Data helper

  12. val DefaultFixPointConfig: FixPointConfig
  13. implicit def DoubleToBuilder(value: Double): DoubleBuilder
  14. implicit def EnumCtoEnumC2[T <: SpinalEnum, T2 <: T](craft: SpinalEnumCraft[T2]): SpinalEnumCraft[T]
  15. implicit def EnumCtoEnumC3[T <: SpinalEnum, T2 <: T](craft: SpinalEnumCraft[T]): SpinalEnumCraft[T2]
  16. implicit def EnumElementToCraft[T <: SpinalEnum](element: SpinalEnumElement[T]): SpinalEnumCraft[T]
  17. implicit def EnumEtoEnumE2[T <: SpinalEnum, T2 <: T](element: SpinalEnumElement[T2]): SpinalEnumElement[T]

    Implicit senum conversion

  18. implicit def EnumEtoEnumE3[T <: SpinalEnum, T2 <: T](element: SpinalEnumElement[T]): SpinalEnumElement[T2]
  19. def False(implicit loc: Location): Bool

    Hardware false value

  20. def FixedFrequency(value: HertzNumber): core.ClockDomain.FixedFrequency
  21. implicit def IntPimped(that: Int): IntPimped
  22. implicit def IntToBits(that: Int): Bits
  23. implicit def IntToBuilder(value: Int): IntBuilder

    Implicit Int/BigInt/Double to Builder

  24. implicit def IntToSInt(that: Int): SInt
  25. implicit def IntToUInt(that: Int): UInt

    Implicit conversion from Int/BigInt/String to UInt/SInt/Bits

  26. implicit def LongToBits(that: Long): Bits
  27. implicit def LongToSInt(that: Long): SInt
  28. implicit def LongToUInt(that: Long): UInt
  29. val LowCostFixPointConfig: FixPointConfig
  30. def SFix(peak: ExpNumber, resolution: ExpNumber): SFix
    Definition Classes
    SFixFactory
  31. def SFix(peak: ExpNumber, width: BitCount): SFix
    Definition Classes
    SFixFactory
  32. def SInt(width: BitCount): SInt

    Create a new SInt of a given width

    Create a new SInt of a given width

    Definition Classes
    SIntFactory
  33. def SInt(u: Unit = ()): SInt

    Create a new SInt

    Create a new SInt

    Definition Classes
    SIntFactory
  34. def True(implicit loc: Location): Bool

    Hardware true value

  35. def UFix(peak: ExpNumber, resolution: ExpNumber): UFix
    Definition Classes
    UFixFactory
  36. def UFix(peak: ExpNumber, width: BitCount): UFix
    Definition Classes
    UFixFactory
  37. def UInt(width: BitCount): UInt

    Create a new UInt of a given width

    Create a new UInt of a given width

    Definition Classes
    UIntFactory
  38. def UInt(u: Unit = ()): UInt

    Create a new UInt

    Create a new UInt

    Definition Classes
    UIntFactory
  39. def UnknownFrequency(): core.ClockDomain.UnknownFrequency
  40. def Vec[T <: Data](firstElement: T, followingElements: T*): Vec[T]
    Definition Classes
    VecFactory
  41. def Vec[T <: Data](gen: HardType[T], size: Int): Vec[T]
    Definition Classes
    VecFactory
  42. def Vec[T <: Data](gen: ⇒ T, size: Int): Vec[T]
    Definition Classes
    VecFactory
  43. def Vec[T <: Data](elements: TraversableOnce[T], dataType: HardType[T] = null): Vec[T]
    Definition Classes
    VecFactory
  44. val Vec: VecBuilder
    Definition Classes
    VecFactory
  45. implicit def VecBitwisePimped[T <: Data with BitwiseOp[T]](that: Vec[T]): VecBitwisePimper[T]
  46. def assert(assertion: Bool, message: Seq[Any], severity: AssertNodeSeverity)(implicit loc: Location): AssertStatement
  47. def assert(assertion: Bool, message: String, severity: AssertNodeSeverity)(implicit loc: Location): AssertStatement
  48. def assert(assertion: Bool, message: Seq[Any])(implicit loc: Location): AssertStatement
  49. def assert(assertion: Bool, message: String)(implicit loc: Location): AssertStatement
  50. def assert(assertion: Bool, severity: AssertNodeSeverity)(implicit loc: Location): AssertStatement
  51. def assert(assertion: Bool)(implicit loc: Location): AssertStatement
  52. final def assert(assertion: Boolean, message: ⇒ Any)(implicit loc: Location): Unit
    Annotations
    @elidable( ASSERTION ) @inline()
  53. def assert(assertion: Boolean): Unit

    Assertion

    Assertion

    Annotations
    @elidable( ASSERTION )
  54. def assume(assertion: Bool)(implicit loc: Location): AssertStatement
  55. def assumeInitial(assertion: Bool)(implicit loc: Location): AssertStatement
  56. def cover(assertion: Bool)(implicit loc: Location): AssertStatement
  57. implicit lazy val implicitConversions: implicitConversions

    Scala implicit

  58. def postTypeFactory[T <: Data](that: T): T
    Definition Classes
    TypeFactory
  59. implicit lazy val postfixOps: postfixOps
  60. implicit lazy val reflectiveCalls: reflectiveCalls
  61. def report(message: Seq[Any], severity: AssertNodeSeverity, includeSourceLocation: Boolean, sourceLocationFormat: String)(implicit loc: Location): AssertStatement
  62. def report(message: String, severity: AssertNodeSeverity, includeSourceLocation: Boolean, sourceLocationFormat: String)(implicit loc: Location): AssertStatement
  63. def report(message: Seq[Any], severity: AssertNodeSeverity, includeSourceLocation: Boolean)(implicit loc: Location): AssertStatement
  64. def report(message: String, severity: AssertNodeSeverity, includeSourceLocation: Boolean)(implicit loc: Location): AssertStatement
  65. def report(message: Seq[Any], severity: AssertNodeSeverity)(implicit loc: Location): AssertStatement
  66. def report(message: String, severity: AssertNodeSeverity)(implicit loc: Location): AssertStatement
  67. def report(message: Seq[Any], includeSourceLocation: Boolean, sourceLocationFormat: String)(implicit loc: Location): AssertStatement
  68. def report(message: String, includeSourceLocation: Boolean, sourceLocationFormat: String)(implicit loc: Location): AssertStatement
  69. def report(message: Seq[Any], includeSourceLocation: Boolean)(implicit loc: Location): AssertStatement
  70. def report(message: String, includeSourceLocation: Boolean)(implicit loc: Location): AssertStatement
  71. def report(message: Seq[Any])(implicit loc: Location): AssertStatement
  72. def report(message: String)(implicit loc: Location): AssertStatement
  73. implicit def tupleBunder10Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10)): TupleBundle10[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10]
  74. implicit def tupleBunder11Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11)): TupleBundle11[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11]
  75. implicit def tupleBunder12Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12)): TupleBundle12[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12]
  76. implicit def tupleBunder13Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13)): TupleBundle13[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13]
  77. implicit def tupleBunder14Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14)): TupleBundle14[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14]
  78. implicit def tupleBunder15Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15)): TupleBundle15[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15]
  79. implicit def tupleBunder16Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16)): TupleBundle16[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16]
  80. implicit def tupleBunder17Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17)): TupleBundle17[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17]
  81. implicit def tupleBunder18Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18)): TupleBundle18[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18]
  82. implicit def tupleBunder19Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19)): TupleBundle19[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19]
  83. implicit def tupleBunder20Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20)): TupleBundle20[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20]
  84. implicit def tupleBunder21Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data, T21 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21)): TupleBundle21[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21]
  85. implicit def tupleBunder22Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data, T10 <: Data, T11 <: Data, T12 <: Data, T13 <: Data, T14 <: Data, T15 <: Data, T16 <: Data, T17 <: Data, T18 <: Data, T19 <: Data, T20 <: Data, T21 <: Data, T22 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22)): TupleBundle22[T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22]
  86. implicit def tupleBunder2Pimp[T1 <: Data, T2 <: Data](pimped: (T1, T2)): TupleBundle2[T1, T2]
  87. implicit def tupleBunder3Pimp[T1 <: Data, T2 <: Data, T3 <: Data](pimped: (T1, T2, T3)): TupleBundle3[T1, T2, T3]
  88. implicit def tupleBunder4Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data](pimped: (T1, T2, T3, T4)): TupleBundle4[T1, T2, T3, T4]
  89. implicit def tupleBunder5Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data](pimped: (T1, T2, T3, T4, T5)): TupleBundle5[T1, T2, T3, T4, T5]
  90. implicit def tupleBunder6Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data](pimped: (T1, T2, T3, T4, T5, T6)): TupleBundle6[T1, T2, T3, T4, T5, T6]
  91. implicit def tupleBunder7Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7)): TupleBundle7[T1, T2, T3, T4, T5, T6, T7]
  92. implicit def tupleBunder8Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8)): TupleBundle8[T1, T2, T3, T4, T5, T6, T7, T8]
  93. implicit def tupleBunder9Pimp[T1 <: Data, T2 <: Data, T3 <: Data, T4 <: Data, T5 <: Data, T6 <: Data, T7 <: Data, T8 <: Data, T9 <: Data](pimped: (T1, T2, T3, T4, T5, T6, T7, T8, T9)): TupleBundle9[T1, T2, T3, T4, T5, T6, T7, T8, T9]
  94. object AF
  95. object AFix
  96. object AFixRounding extends ScopeProperty[TagAFixTruncated]
  97. object ASYNC extends ResetKind
  98. object AllowMixedWidth extends SpinalTag
  99. object AllowPartialyAssignedTag extends SpinalTag
  100. object Analog

    Set a data to Analog

  101. object AnnotationUtils
  102. object ArrayManager
  103. object B extends BitVectorLiteralFactory[Bits]

    Used to create a new Bits or cast to Bits

  104. object BIG extends Endianness

    Big-Endian

  105. object BOOT extends ResetKind
  106. object BaseType
  107. object COMMENT_ATTRIBUTE extends AttributeKind
  108. object COMMENT_TYPE_ATTRIBUTE extends AttributeKind
  109. object Cat

    Concatenate a list of data

  110. object ClassName
  111. object Clock
  112. object ClockDomain extends Serializable
  113. object ClockDomainStack extends ScopeProperty[Handle[ClockDomain]]
  114. object CombInit

    Create a new signal, assigned by the given parameter.

    Create a new signal, assigned by the given parameter.

    Useful to provide a "copy" of something that you can then modify with more conditional assignments.

    See also

    CombInit Documentation

  115. object Component
  116. object ConditionalContext
  117. object ContextSwapper
  118. object CyclesCount extends Serializable
  119. object DEFAULT_ATTRIBUTE extends AttributeKind
  120. object Data
  121. object DataAssign
  122. object Device extends Serializable
  123. object Driver
  124. object DslScopeStack extends ScopeProperty[ScopeStatement]
  125. object DummyObject extends DummyTrait
  126. object ERROR extends AssertNodeSeverity
  127. object FAILURE extends AssertNodeSeverity
  128. object FALLING extends EdgeKind
  129. object FixPointProperty extends ScopeProperty[FixPointConfig]
  130. object GenerationFlags
  131. object GlobalData
  132. object Gray
  133. object HIGH extends Polarity
  134. object HardMap
  135. object HardType
  136. object ImplicitArea
  137. object Info
  138. object InitAssign
  139. object InitialAssign
  140. object IsInterface extends SpinalTag
  141. object LITTLE extends Endianness

    Little-Endian

  142. object LOW extends Polarity
  143. object Language
  144. object Latch
  145. object LatchWhen
  146. object LocatedPendingError
  147. object LutInputs extends ScopeProperty[Int]
  148. object MaskedLiteral
  149. object Mem
  150. object MemReadAsync
  151. object MemReadSync
  152. object MemReadWrite
  153. object MemWrite
  154. object Mux

    SpinalHDL standalone mux with Bool selector

    SpinalHDL standalone mux with Bool selector

    Types like Enum/Bool/Bits/UInt/SInt can also be used as selector with the method mux() of their parent BaseType.

    See also

    Mux documentation

  155. object NOTE extends AssertNodeSeverity
  156. object Nameable
  157. object NamedType
  158. object OnCreateStack extends ScopeProperty[(Nameable) ⇒ Unit]
  159. object OwnableRef
  160. object PendingError
  161. object Pull
  162. object REPORT_TIME
  163. object RISING extends EdgeKind
  164. object Ram_1w_1ra
  165. object Ram_1w_1rs
  166. object Reg

    Declare a register with a signal type.

    Declare a register with a signal type.

    Example: 

    1. val reg1 = Reg(UInt(4 bits))
    See also

    Register documentation

  167. object RegInit

    Declare a register with an initialize value.

    Declare a register with an initialize value.

    Example: 

    1. // UInt register of 4 bits initialized with 0 when the reset occurs
val reg = RegInit(U"0000")
    See also

    Register documentation

  168. object RegNext

    Register a signal by one clock.

    Register a signal by one clock.

    Example: 

    1. val reg1 = Reg(UInt(4 bits))
// Register that updates itself every cycle with a sample of reg1 incremented by 1
 val reg2 = RegNext(reg1 + 1)
    See also

    Register documentation

  169. object RegNextWhen

    Register a signal when a condition is true.

    Register a signal when a condition is true.

    See also

    Register documentation

  170. object ReportSourceLocation
  171. object RoundType
  172. object S extends BitVectorLiteralFactory[SInt]

    Used to create a new SInt or cast to SInt

  173. object SF
  174. object SFix2D

    Two-dimensional SFix

  175. object SQ
  176. object SYNC extends ResetKind
  177. object ScalaLocated
  178. object ScopeProperty
  179. object Select
  180. object Spinal
  181. object SpinalConfig extends Serializable
  182. object SpinalEnumEncoding

    Used to create a custom encoding

    Used to create a custom encoding

    Example: 

    1. object BR extends SpinalEnum{
  val NE, EQ, J, JR = newElement()
  defaultEncoding = SpinalEnumEncoding("opt")(
      EQ -> 0,
      NE -> 1,
      J  -> 2,
      JR -> 3 )
}
  183. object SpinalError
  184. object SpinalExit extends Serializable
  185. object SpinalInfo
  186. object SpinalLog
  187. object SpinalMap

    Spinal map

  188. object SpinalProgress
  189. object SpinalSystemVerilog
  190. object SpinalTagReady
  191. object SpinalVerilog
  192. object SpinalVhdl
  193. object SpinalWarning
  194. object SwitchStack extends ScopeProperty[SwitchContext]
  195. object SystemVerilog extends SpinalMode
  196. object TimingEndpointType
  197. object TupleBundle
  198. object U extends BitVectorLiteralFactory[UInt]

    Used to create a new UInt or cast to UInt

  199. object UF
  200. object UFix2D

    Two-dimensional UFix

  201. object UInt2D extends Serializable
  202. object UQ
  203. object UnionElement
  204. object VHDL extends SpinalMode
  205. object Verilator
  206. object Verilog extends SpinalMode
  207. object WARNING extends AssertNodeSeverity
  208. object addDefaultGenericValue extends SpinalTag

    In VHDL add the generic value in the definition of the blackbox

  209. object allowAssignmentOverride extends SpinalTag
  210. object allowDirectionLessIoTag extends SpinalTag
  211. object allowFloating extends SpinalTag
  212. object allowOutOfRangeLiterals extends SpinalTag
  213. object auto extends MemTechnologyKind
  214. object binaryOneHot extends SpinalEnumEncoding

    Binary One hot encoding

    Binary One hot encoding

    Example: 

    1. 001, 010, 100
  215. object binarySequential extends SpinalEnumEncoding

    Binary Sequential

    Binary Sequential

    Example: 

    1. 000, 001, 010, 011, 100, 101, ....
  216. object blackboxAll extends MemBlackboxingPolicy

    Blackbox all memory.

    Blackbox all memory.

    Throw an error on unblackboxable memory.

    See also

    RAM/ROM Blackboxing policy documentation

  217. object blackboxAllWhatsYouCan extends MemBlackboxingPolicy

    Blackbox every memory that is replaceable.

    Blackbox every memory that is replaceable.

    See also

    RAM/ROM Blackboxing policy documentation

  218. object blackboxByteEnables extends MemBlackboxingPolicy

    Blackbox every memory which use write port with byte mask.

    Blackbox every memory which use write port with byte mask.

    Useful because synthesis tool don't support an unified way to infer byte mask in verilog/VHDL. Throw an error on unblackboxable memory.

    See also

    RAM/ROM Blackboxing policy documentation

  219. object blackboxOnlyIfRequested extends MemBlackboxingPolicy

    Blackbox memory specified by the user.

    Blackbox memory specified by the user.

    Throw an error on unblackboxable memory.

    See also

    RAM/ROM Blackboxing policy documentation

  220. object blackboxRequestedAndUninferable extends MemBlackboxingPolicy

    Blackbox memory specified by the user and memory that is known to be uninferable (mixed-width, …).

    Blackbox memory specified by the user and memory that is known to be uninferable (mixed-width, …).

    Throw an error on unblackboxable memory.

    See also

    RAM/ROM Blackboxing policy documentation

  221. object cloneOf

    Return a new data with the same data structure as the given parameter (including bit width)

  222. object crossClockBuffer extends SpinalTag
  223. object crossClockDomain extends SpinalTag

    Tag for clock crossing signals

    Tag for clock crossing signals

    See also

    Clock domain crossing documentation

  224. object default

    default statement of a SpinalHDL switch/ case

    default statement of a SpinalHDL switch/ case

    See also

    switch Documentation

  225. object distributedLut extends MemTechnologyKind
  226. object doRead extends DuringWritePolicy
  227. object dontCare extends ReadUnderWritePolicy with DuringWritePolicy

    Don’t care about the read value when the case occurs

  228. object dontObfuscate extends SpinalTag
  229. object dontRead extends DuringWritePolicy
  230. object eitherFirst extends ReadUnderWritePolicy with DuringWritePolicy
  231. object getFixRound
  232. object getFixSym
  233. object globalCache
  234. object graySequential extends SpinalEnumEncoding

    Gray encoding (sequentially assigned)

    Gray encoding (sequentially assigned)

    Example: 

    1. 000, 001, 011, 010, ...
    Note

    If used in FSM it is not ensured that only gray encoding preserving transitions are done. If that is needed e.g. for CDC reasons, the transitions must be checked manually.

  235. object ifGen
  236. object in extends IODirection

    Declare an input port

    Declare an input port

    See IODirection for syntax help.

  237. object inferred extends SpinalEnumEncoding

    Inferred encoding

  238. object inout extends IODirection

    Declare an inout port

    Declare an inout port

    See IODirection for syntax help.

  239. object is

    is statement of a SpinalHDL switch/ case

    is statement of a SpinalHDL switch/ case

    See also

    switch Documentation

  240. object isPow2

    Check if a number is a power of 2

  241. object log2Up

    Give number of bit to encode a given number of states

  242. object native extends SpinalEnumEncoding

    Native encoding

  243. object noBackendCombMerge extends SpinalTag
  244. object noCombinatorialLoopCheck extends SpinalTag
  245. object noInit extends SpinalTag
  246. object noLatchCheck extends SpinalTag
  247. object noNumericType extends SpinalTag

    Transform all unsigned/signed into std_logic_vector

  248. object out extends IODirection

    Declare an output port

    Declare an output port

    See IODirection for syntax help.

  249. object ramBlock extends MemTechnologyKind
  250. object randomBoot extends SpinalTag
  251. object readFirst extends ReadUnderWritePolicy

    The read will get the old value (before the write)

  252. object registerFile extends MemTechnologyKind
  253. object reportIncludeSourceLocation extends SpinalTag
  254. object roundUp

    Round up a BigInt

  255. object signalCache
  256. object switch

    case/switch SpinalHDL statement

    case/switch SpinalHDL statement

    Example: 

    1. switch(x) {
    is(value1) {
        // execute when x === value1
    }
    is(value2) {
        // execute when x === value2
    }
    default {
       // execute if none of precedent conditions are meet
    }
 }
    See also

    switch Documentation

  257. object tagAFixResized extends SpinalTag
  258. object tagAutoResize extends SpinalTag
  259. object tagTruncated extends SpinalTag
  260. object uLogic extends SpinalTag

    Create a Ulogic tag used by Blackbox in order to transform std_logic into std_ulogic

  261. object unsetRegIfNoAssignementTag extends SpinalTag
  262. object unusedTag extends SpinalTag
  263. object weakCloneOf

    Return a new data with the same data structure as the given parameter (except bit width)

  264. object when

    Allow to express hardware conditional statements based on a Bool expression like an if.

    Allow to express hardware conditional statements based on a Bool expression like an if.

    Example: 

    1. when(cond1) {
  myCnt := 0
}elsewhen(cond2) {
  myCnt := myCnt + 1
}otherwise {
  myCnt := myCnt - 1
}
    See also

    when Documentation

  265. object widthOf

    Return the number of bit of the given data

  266. object writeFirst extends ReadUnderWritePolicy

    The read will get the new value (provided by the write)

Deprecated Value Members

  1. def Bool: Bool

    Deprecated, use Bool() (with braces) instead

    Deprecated, use Bool() (with braces) instead

    Definition Classes
    BoolFactory
    Annotations
    @deprecated
    Deprecated

    Use Bool() (with braces) instead

  2. def toSFix(sint: SInt): SFix
    Definition Classes
    SFixCast
    Annotations
    @deprecated
    Deprecated

    (Since version ???) Use xxx.toSFix instead

  3. def toUFix(uint: UInt): UFix
    Definition Classes
    UFixCast
    Annotations
    @deprecated
    Deprecated

    (Since version ???) Use xxx.toUFix instead

  4. object Sel

    Sel operation

    Sel operation

    Annotations
    @deprecated
    Deprecated

    (Since version ???) Use Select instead

  5. object cloneable
    Annotations
    @deprecated
    Deprecated

    (Since version ???) Use HardType instead

  6. object inWithNull extends IODirection
    Annotations
    @deprecated
    Deprecated

    Use apply or port instead: 'val b = in(maybeNull)' or 'val rgb = in port maybeNull'

  7. object outWithNull extends IODirection
    Annotations
    @deprecated
    Deprecated

    Use apply or port instead: 'val b = out(maybeNull)' or 'val rgb = out port maybeNull'

  8. object wrap
    Annotations
    @deprecated
    Deprecated

    (Since version ???) Use HardType instead

Inherited from BaseTypeCast

Inherited from UFixCast

Inherited from SFixCast

Inherited from BaseTypeFactory

Inherited from UFixFactory

Inherited from SFixFactory

Inherited from TypeFactory

Inherited from VecFactory

Inherited from SIntFactory

Inherited from UIntFactory

Inherited from BitsFactory

Inherited from BoolFactory

Inherited from AnyRef

Inherited from Any

Ungrouped