Packages

t

spinal.core

ValCallbackRec

trait ValCallbackRec extends ValCallback

The Bundle is a composite type that defines a group of named signals (of any SpinalHDL basic type) under a single name. The Bundle can be used to model data structures, buses and interfaces.

Example: 

  1. val cmd = new Bundle{
  val init   = in Bool()
  val start  = in Bool()
  val result = out Bits(32 bits)
}
See also

Bundle Documentation

Linear Supertypes
ValCallback, AnyRef, Any
Known Subclasses
Area, AreaObject, AreaRoot, BlackBox, BlackBoxULogic, BoolEdges, Bundle, BundleCase, ClockEnableArea, ClockingArea, Component, Composite, ImplicitArea, Interface, MemWritePayload, Ram_1w_1ra, Ram_1w_1rs, Ram_1wors, Ram_1wrs, Ram_2c_1w_1rs, Ram_2wrs, ResetArea, SFix2D, SlowArea, SpinalStruct, TupleBundle1, TupleBundle10, TupleBundle11, TupleBundle12, TupleBundle13, TupleBundle14, TupleBundle15, TupleBundle16, TupleBundle17, TupleBundle18, TupleBundle19, TupleBundle2, TupleBundle20, TupleBundle21, TupleBundle22, TupleBundle3, TupleBundle4, TupleBundle5, TupleBundle6, TupleBundle7, TupleBundle8, TupleBundle9, TupleBundleBase, UFix2D, UInt2D, Fiber, Fence, Lockable, RetainerGroup, BufferCC, Counter, CounterUpDown, DataOr, Flow, FlowCCUnsafeByToggle, FlowCmdRsp, Fragment, HistoryModifyable, MemReadPort, MemReadPortAsync, MemReadStreamFlowPort, MemReadWritePort, MemWriteCmd, MemWriteCmdWithMask, NoData, PackedBundle, PackedWordBundle, PulseCCByToggle, ReadRetLinked, ResetAggregator, ResetCtrlFiber, ResetHolder, Stream, StreamArbiter, StreamCCByToggle, StreamDemux, StreamFifo, CounterUpDownFmax, StreamFifoCC, StreamFifoLowLatency, StreamFifoMultiChannelPop, StreamFifoMultiChannelPush, StreamFifoMultiChannelSharedSpace, StreamFlowArbiter, StreamFork, StreamForkArea, StreamFragmentBitsDispatcher, StreamHistory, StreamMux, StreamPacker, StreamToStreamFragmentBits, StreamTransactionCounter, StreamTransactionExtender, StreamUnpacker, Timeout, Wrapper, VJTAG, sld_virtual_jtag, EG_LOGIC_BUFG, EG_LOGIC_ODDR, EG_PHY_BRAM, EG_PHY_BRAM32K, EG_PHY_SDRAM_2M_32, BB, DCCA, EHXPLLL, IDDRX1F, IFS1P3BX, JTAGG, JtaggIo, ODDRX1F, OFS1P3BX, TSFF, Ulx3sUsrMclk, ICE40_PLL, SB_DFFR, SB_DFFS, SB_GB, SB_IO, SB_PLL40_CORE, SB_PLL40_PAD, SB_SPRAM256KA, BSCANE2, BUFG, BUFGCE, BUFIO, FDRE, IBUF, IBUFG, IDELAYCTRL, IDELAYE2, IOBUF, IOBUFDS, ISERDESE2, MMCME2_BASE, Mmcme2Ctrl, Mmcme2CtrlGenerator, Mmcme2Dbus, OBUFDS, ODELAYE2, OSERDESE2, PLLE2_BASE, STARTUPE2, AhbLite3, AhbLite3Arbiter, AhbLite3Decoder, AhbLite3Master, AhbLite3OnChipRam, AhbLite3OnChipRamMultiPort, AhbLite3OnChipRom, AhbLite3SlaveFactory, AhbLite3ToApb3Bridge, DefaultAhbLite3Slave, Apb3, Apb3CC, Cmd, Rsp, Apb3CCToggle, Apb3Decoder, Apb3Dummy, Apb3Gpio, Apb3Router, Apb3SlaveFactory, Apb4, Apb4Hub, Apb4SlaveFactory, Axi4, Axi4Ar, Axi4ArUnburstified, Axi4Arw, Axi4ArwUnburstified, Axi4Aw, Axi4AwUnburstified, Axi4Ax, Axi4AxUnburstified, Axi4B, Axi4CC, Axi4Downsizer, Axi4DownsizerSubTransactionGenerator, Axi4IdRemover, Axi4R, Axi4ReadOnly, Axi4ReadOnlyAligner, Context, Axi4ReadOnlyArbiter, Axi4ReadOnlyCC, Axi4ReadOnlyChecker, Axi4ReadOnlyCompactor, Context, Axi4ReadOnlyDecoder, Axi4ReadOnlyDownsizer, Axi4ReadOnlyErrorSlave, Axi4ReadOnlyIdRemover, Axi4ReadOnlyOnePerId, Axi4ReadOnlyToTilelink, Axi4ReadOnlyToTilelinkFull, Axi4ReadOnlyUnburster, Axi4ReadOnlyUpsizer, RspContext, Axi4Shared, Axi4SharedArbiter, Axi4SharedCC, Axi4SharedChecker, Axi4SharedDecoder, Axi4SharedErrorSlave, Axi4SharedIdRemover, Axi4SharedOnChipRam, Axi4SharedOnChipRamMultiPort, Axi4SharedOnChipRamPort, Axi4SharedToApb3Bridge, Axi4SharedToAxi3Shared, Axi4SharedToBram, Axi4SlaveFactory, Axi4ToTilelinkFiber, Axi4Upsizer, Axi4W, Axi4WriteOnly, Axi4WriteOnlyAligner, Context, WCmd, Axi4WriteOnlyArbiter, Axi4WriteOnlyCC, Axi4WriteOnlyCompactor, Context, Axi4WriteOnlyDecoder, Axi4WriteOnlyDownsizer, Axi4WriteOnlyErrorSlave, Axi4WriteOnlyIdRemover, Axi4WriteOnlyOnePerId, Axi4WriteOnlyToTilelink, Axi4WriteOnlyToTilelinkFull, Axi4WriteOnlyUnburster, Axi4WriteOnlyUpsizer, FormalAxi4Record, UnbursterIDManager, IdLen, IdResp, AxiLite4, AxiLite4Ax, AxiLite4B, AxiLite4R, AxiLite4ReadOnly, AxiLite4SimpleReadDma, AxiLite4SimpleReadDmaCmd, AxiLite4SlaveFactory, AxiLite4W, AxiLite4WriteOnly, Axi4StreamBundle, Axi4StreamSimpleWidthAdapter, Axi4StreamSparseCompactor, Axi4StreamWidthAdapter, Axi4StreamWidthAdapter_8_8, AvalonMM, AvalonMMSlaveFactory, AvalonReadDma, AvalonReadDmaCmd, AvalonST, AvalonSTDelayAdapter, AvalonSTPayload, Axi4SharedToBmb, Bmb, BmbAck, BmbAlignedSpliter, Context, BmbAligner, BmbArbiter, BmbBridgeGenerator, BmbCcFifo, BmbCcToggle, BmbClintGenerator, BmbCmd, BmbContextRemover, Ctx, BmbDecoder, BmbDecoderOutOfOrder, SourceHistory, BmbDecoderPerSource, BmbDownSizerBridge, OutputContext, BmbEg4S20Bram32K, BmbErrorSlave, BmbExclusiveMonitor, BmbExclusiveMonitorGenerator, BmbIce40Spram, BmbInterconnectGenerator, ConnectionModel, MasterModel, SlaveModel, BmbInv, BmbInvalidateMonitor, Context, BmbInvalidateMonitorGenerator, BmbInvalidationArbiter, BmbLengthFixer, Context, BmbOnChipRam, BmbOnChipRamMultiPort, BmbPlicGenerator, BmbRsp, BmbSlaveFactory, BmbSourceDecoder, BmbSourceRemover, Context, BmbSync, BmbSyncRemover, Context, BmbToApb3Bridge, BmbToApb3Generator, BmbToAxi4ReadOnlyBridge, BmbToAxi4SharedBridge, Info, BmbToAxi4SharedBridgeAssumeInOrder, Info, BmbToAxi4WriteOnlyBridge, BmbToWishbone, BmbUnburstify, Context, BmbUpSizerBridge, OutputContext, BmbWriteRetainer, BRAM, BRAMDecoder, BRAMSlaveFactory, BsbDownSizerAlignedMultiWidth, BsbDownSizerSparse, BsbInterconnectGenerator, ConnectionModel, MasterModel, SlaveModel, BsbTransaction, BsbUpSizerDense, BsbUpSizerSparse, MappedConnection, NegotiateSP, Node, BusSlaveFactory, BusSlaveFactoryAddressWrapper, BusSlaveFactoryDelayed, AhbLite3BusInterface, Apb3BusInterface, Apb4BusInterface, AxiLite4BusInterface, BRAMBusInterface, BusIf, BusIfBase, WishboneBusInterface, AsyncMemoryBus, AsyncMemoryBusFactory, PipelinedMemoryBus, PipelinedMemoryBusArbiter, PipelinedMemoryBusCmd, PipelinedMemoryBusDecoder, PipelinedMemoryBusRsp, PipelinedMemoryBusSlaveFactory, PipelinedMemoryBusToApbBridge, Arbiter, Axi4Bridge, AxiLite4Bridge, Bus, BusFragment, ChannelA, ChannelB, ChannelC, ChannelD, ChannelE, ContextAsyncBufferBase, ContextAsyncBufferFull, ContextBufferAdd, ContextBufferQuery, ContextBufferRemove, Decoder, ErrorSlave, FifoCc, Opcode, Ram, ScopeFiber, SlaveFactory, TransferFilter, WidthAdapter, ChannelDownSizer, ChannelUpSizer, Cache, Cache, CtrlCmd, CtxDownD, GeneralSlot, LineCtrl, ProberCmd, ProberSlot, PutMergeCmd, ReadBackendCmd, ReadDownCmd, Slot, SlotPool, Tags, WriteBackendCmd, CacheFiber, ChannelDataBuffer, DataPayload, Hub, CtxA, CtxC, DataPayload, ProbeCmd, ProbeCtx, ProbeCtxFull, HubFiber, OrderingCmd, Axi4Bridge, AxiLite4Bridge, Connection, ConnectionRaw, Interleaver, MasterBus, Node, NodeM2s, NodeRaw, NodeS2m, NodeUpDown, RamFiber, SlaveBus, SlaveBusAny, TransferFilter, WidthAdapter, TilelinkTestbenchBase, Wishbone, WishboneAdapter, WishboneArbiter, WishboneDecoder, WishboneGpio, WishboneSlaveFactory, WishboneToBmb, WishboneToBmbGenerator, BmbMacEth, Crc, MacEth, MacEthCtrl, MacRxAligner, MacRxBuffer, MacRxChecker, MacRxPreamble, MacTxAligner, MacTxBuffer, MacTxCrc, MacTxHeader, MacTxInterFrame, MacTxManagedStreamFifoCc, MacTxPadder, Mdio, Mii, MiiRx, MiiTx, PhyIo, PhyRx, PhyTx, Rmii, RmiiRx, RmiiTx, Apb3I2cCtrl, BmbI2cCtrl, I2c, I2cAddress, I2cIoFilter, I2cSlave, I2cSlaveBus, I2cSlaveCmd, I2cSlaveConfig, I2cSlaveIo, I2cSlaveRsp, I2cSoftMaster, Jtag, JtagFsm, JtagInstructionDebuggerGenerator, JtagInstructionWrapper, JtagTap, JtagTapDebuggerGenerator, JtagTapInstructionCtrl, JtagTapInstructionFlowFragmentPush, JtagTapInstructionIdcode, JtagTapInstructionRead, JtagTapInstructionReadWrite, JtagTapInstructionWrite, SimpleJtagTap, VJtag2BmbMaster, VJtag2BmbMasterGenerator, VjtagTap, JtagTap, JtagTapInstructionFlowFragmentPush, JtagTapInstructionRead, JtagTapInstructionReadWrite, JtagTapInstructionWrite, JtaggShifter, SimpleJtagTap, Bscane2BmbMaster, Bscane2BmbMasterGenerator, Decoder, Encoder, Sio, Apb3SpiMasterCtrl, Apb3SpiSlaveCtrl, SpiHalfDuplexMaster, SpiKind, SpiMaster, SpiMasterCmd, SpiMasterCtrl, SpiMasterCtrlCmdData, SpiMasterCtrlCmdSs, SpiMasterCtrlConfig, SpiSlave, SpiSlaveCtrl, SpiSlaveCtrlIo, WishboneSpiMasterCtrl, WishboneSpiSlaveCtrl, Apb3SpiXdrMasterCtrl, BmbSpiXdrMasterCtrl, SpiXdrMaster, SpiIce40, Cmd, Config, Rsp, TopLevel, XipBus, XipCmd, XdrOutput, XdrPin, Apb3UartCtrl, AvalonMMUartCtrl, BmbUartCtrl, TilelinkUartCtrl, TilelinkUartFiber, Uart, UartCtrl, UartCtrlConfig, UartCtrlFrameConfig, UartCtrlIo, UartCtrlRx, UartCtrlTx, UartCtrlUsageExample, WishboneUartCtrl, UsbDataRxFsm, UsbDataTxFsm, UsbTimer, UsbTokenRxFsm, UsbTokenTxFsm, UsbOhci, UsbOhciAxi4, UsbOhciGenerator, UsbOhciWishbone, UsbDevicePhyNative, UsbHostManagementIo, Ctrl, CtrlCc, CtrlPort, CtrlRx, CtrlRxPayload, UsbLsFsPhy, Timeout, UsbLsFsPhyAbstractIo, UsbLsFsPhyFilter, UsbPhyFsNativeIo, UsbDeviceBmbGenerator, UsbDeviceCtrl, PhyCc, PhyIo, Rx, Tx, UsbDeviceWithPhyWishbone, DebugBus, DebugBusSlaveFactory, DebugCapture, DebugCmd, DebugDmToHart, DebugHartBus, DebugHartToDm, DebugModule, DebugModuleFiber, DebugRsp, DebugTransportModuleJtag, DebugTransportModuleJtagTap, DebugTransportModuleJtagTapWithTunnel, DebugTransportModuleTunneled, DebugUpdate, JtagTunnel, Alu, BranchPredictorLine, CoreDataBus, CoreDataCmd, CoreDecodeOutput, CoreExecute0Output, CoreExecute1Output, CoreFetchOutput, CoreInstructionBus, CoreInstructionCmd, CoreInstructionRsp, CoreWriteBack0Output, DataCache, LineInfo, DataCacheCpuBus, DataCacheCpuCmd, DataCacheCpuRsp, DataCacheMemBus, DataCacheMemCmd, DataCacheMemRsp, InstructionCache, LineInfo, InstructionCacheCpuBus, InstructionCacheCpuCmd, InstructionCacheCpuRsp, InstructionCacheFlushBus, TopLevel, InstructionCacheMemBus, InstructionCacheMemCmd, InstructionCacheMemRsp, RiscvCore, IMM, InstructionCtrl, TopLevel, TopLevel, RiscvAhbLite3, RiscvAvalon, RiscvAxi4, DebugExtensionBus, DebugExtensionCmd, DebugExtensionIo, DebugExtensionRsp, alt_inbuf, alt_inbuf_diff, alt_outbuf, alt_outbuf_diff, alt_outbuf_tri, alt_outbuf_tri_diff, ApbCmd, Block, Ctrl, CtrlCmd, Mem, MemCmd, SblCmd, SblReadCmd, SblReadDma, SblReadDmaCmd, SblReadRet, SblWriteCmd, Module, SerialCheckerPhysical, SerialCheckerPhysicalToSerial, SerialCheckerPhysicalfromSerial, SerialCheckerRx, SerialCheckerTx, SerialLinkRx, SerialLinkRxToTx, SerialLinkTx, SerialSafeLayerTx, SerialSafelLayerRx, Floating, FloatingCompareResult, RecFloating, State, StateBoot, StateDelay, StateFsm, StateMachine, LargeExample, TopLevel, TopLevel, TopLevel, TopLevel, StateMachineSlave, TopLevel, TopLevel, TopLevel, TopLevel, TopLevel, TopLevel, TopLevel, TopLevel, StateParallelFsm, Arty7BufgGenerator, ClockDomainResetGenerator, ResetGenerator, ClockDomainResetGeneratorIf, ClockDomainResetGeneratorV2, Generator, GeneratorComponent, Arty7BufgGenerator, ClockDomainResetGenerator, ResetGenerator, Generator, GeneratorComponent, Rgb, VideoDma, VideoDmaMem, TmdsEncoder, VgaToHdmiEcp5, AvalonMMVgaCtrl, Axi4VgaCtrl, BlinkingVgaCtrl, BmbVgaCtrl, BmbVgaCtrlGenerator, Vga, VgaCtrl, HVArea, VgaTimings, VgaTimingsHV, Apb3Gpio2, BmbGpio2, Ctrl, InOutVecToBits, D, E, ReadableOpenDrain, TriState, TriStateArray, TriStateOutput, MixedDivider, MixedDividerCmd, MixedDividerRsp, SignedDivider, SignedDividerCmd, SignedDividerRsp, UnsignedDivider, UnsignedDividerCmd, UnsignedDividerRsp, Dfi, DfiCATrainingInterface, DfiControlInterface, DfiErrorInterface, DfiLevelingTraingInterface, DfiLowPowerControlInterface, DfiPhyRequesetedTrainingInterface, DfiRd, DfiRdCs, DfiReadInterface, DfiReadTrainingInterface, DfiStatusInterface, DfiUpdateInterface, DfiWr, DfiWriteInterface, DfiWriteTrainingInterface, Axi4SharedSdramCtrl, BmbSdramCtrl, Context, SdramCtrl, SdramCtrlAxi4SharedContext, SdramCtrlBackendCmd, SdramCtrlBank, SdramCtrlBus, SdramCtrlCmd, SdramCtrlRsp, SdramInterface, Backend, PipelineCmd, PipelineRsp, BmbAdapter, BmbToCorePort, Context, Core, CoreCmd, CoreConfig, CorePort, CoreRsp, CoreTask, CoreTasks, CoreWriteData, CtrlWithoutPhy, CtrlWithoutPhyBmb, InitCmd, Refresher, SdramAddress, SdramXdrIo, SdramXdrPhyCtrl, SdramXdrPhyCtrlPhase, SoftBus, Tasker, Status, Task, TimingEnforcer, mt41k128m16jt_model, mt48lc16m16a2_model, Ecp5Sdrx2Phy, PLLE2_ADV, RtlPhy, Address, RtlPhyInterface, RtlPhyWriteCmd, SdrInferedPhy, XilinxS7Phy, Apb3Clint, Apb3InterruptCtrl, AxiLite4Clint, BmbClint, Clint, ClintPort, InterruptCtrl, InterruptNode, MachineTimer, MappedClint, Plru, Prescaler, TilelinkClint, TilelinkClintFiber, Timer, WishboneClint, BmbBsbToDeltaSigma, BmbBsbToDeltaSigmaGenerator, BsbToDeltaSigma, SIntToSigmaDeltaSecondOrder, UIntToSigmaDeltaFirstOrder, PDMCore, CtrlLink, Area, CtrlLinkMirror, DirectLink, ForkLink, JoinLink, Link, Node, Area, Node, S2MLink, StageLink, AxiLite4Plic, MappedPlic, PlicGateway, PlicGatewayActiveHigh, PlicTarget, Request, TilelinkPlic, TilelinkPlicFiber, WishbonePlic, FiberPlugin, Pipeline, PipelineTop, Stage, Pinsec, PinsecTimerCtrl, PinsecTimerCtrlExternal, JtagAvalonDebugger, JtagAxi4SharedDebugger, JtagBridge, JtagBridgeNoTap, SystemDebugger, SystemDebuggerMemBus, SystemDebuggerMemCmd, SystemDebuggerRemoteBus, SystemDebuggerRsp, VJtagBridge, DmaMemoryCore, BankWord, DmaMemoryCoreReadBus, DmaMemoryCoreReadCmd, DmaMemoryCoreReadRsp, DmaMemoryCoreWriteBus, DmaMemoryCoreWriteCmd, DmaMemoryCoreWriteRsp, Aggregator, AggregatorCmd, AggregatorRsp, ChannelIo, Core, ArbiterLogic, B2sReadContext, ChannelLogic, InputContext, Interrupt, M2bWriteContext, ReadContext, SgReadContext, SgWriteContext, WriteContext, SgBus, SgCmd, SgRsp, DmaSgGenerator, ChannelModel, InputModel, OutputModel, FlowCCByToggle, StreamDispatcherSequencial
Ordering
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Inherited
  1. ValCallbackRec
  2. ValCallback
  3. AnyRef
  4. Any
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Visibility
  1. Public
  2. All

Abstract Value Members

  1. abstract def valCallbackRec(ref: Any, name: String): Unit

Concrete Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  5. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @HotSpotIntrinsicCandidate()
  6. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  7. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  8. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  9. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  10. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  11. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  12. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  13. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  14. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  15. def toString(): String
    Definition Classes
    AnyRef → Any
  16. def valCallback[T](ref: T, name: String): T
    Definition Classes
    ValCallbackRec → ValCallback
  17. def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit
  18. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  19. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  20. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from ValCallback

Inherited from AnyRef

Inherited from Any

Ungrouped