class WishboneSlaveFactory extends BusSlaveFactoryDelayed

This is the slave facotory fot the wishbone bus

Linear Supertypes
BusSlaveFactoryDelayed, BusSlaveFactory, Area, OverridedEqualsHashCode, ValCallbackRec, ValCallback, NameableByComponent, Nameable, ContextUser, ScalaLocated, GlobalDataUser, OwnableRef, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. WishboneSlaveFactory
  2. BusSlaveFactoryDelayed
  3. BusSlaveFactory
  4. Area
  5. OverridedEqualsHashCode
  6. ValCallbackRec
  7. ValCallback
  8. NameableByComponent
  9. Nameable
  10. ContextUser
  11. ScalaLocated
  12. GlobalDataUser
  13. OwnableRef
  14. AnyRef
  15. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Instance Constructors

  1. new WishboneSlaveFactory(bus: Wishbone, reg_fedback: Boolean = true)

    bus

    the wishbone bus istance that will connect with the module

    reg_fedback

    if set to false, the slave will acknowledge as soon as possible otherwise will wait the next clock cycle(default)

Type Members

  1. abstract type RefOwnerType
    Definition Classes
    OwnableRef

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. val _config: BusSlaveFactoryConfig

    Configuration of the BusSlaveFactory

    Configuration of the BusSlaveFactory

    Attributes
    protected
    Definition Classes
    BusSlaveFactory
  5. val _context: Capture
    Definition Classes
    Area
  6. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  7. val askRead: Bool
  8. val askWrite: Bool
  9. def build(): Unit

    In this function you have to define the read/write logic thanks to element, elementsPerAddress and elementsPerRangeAddress This is the only thing with def busDataWidth that should be implement by class that extends BusSlaveFactoryDelay

    In this function you have to define the read/write logic thanks to element, elementsPerAddress and elementsPerRangeAddress This is the only thing with def busDataWidth that should be implement by class that extends BusSlaveFactoryDelay

    Definition Classes
    WishboneSlaveFactory → BusSlaveFactoryDelayed
  10. def busDataWidth: Int

    Return the data width of the bus

    Return the data width of the bus

    Definition Classes
    WishboneSlaveFactory → BusSlaveFactory
  11. val byteAddress: UInt
  12. def childNamePriority: Byte
    Definition Classes
    Area
  13. def clearOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
    Definition Classes
    BusSlaveFactory
  14. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @IntrinsicCandidate()
  15. def component: Component
    Definition Classes
    ContextUser
  16. def createAndDriveFlow[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, checkByteEnable: Boolean = false): Flow[T]

    Create a writable Flow register of type dataType at address and placed at bitOffset in the word

    Create a writable Flow register of type dataType at address and placed at bitOffset in the word

    checkByteEnable

    do not trigger flow if byte enable is all zero. See https://github.com/SpinalHDL/SpinalHDL/issues/1265 for the discussion about this behaviour.

    Definition Classes
    BusSlaveFactory
  17. def createReadAndClearOnSet[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T
    Definition Classes
    BusSlaveFactory
  18. def createReadAndSetOnSet[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T
    Definition Classes
    BusSlaveFactory
  19. def createReadAndWrite[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    Create a read write register of type dataType at address and placed at bitOffset in the word

    Create a read write register of type dataType at address and placed at bitOffset in the word

    Definition Classes
    BusSlaveFactory
  20. def createReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

    Create multi-words read register of type dataType

    Create multi-words read register of type dataType

    Definition Classes
    BusSlaveFactory
  21. def createReadOnly[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    Create a read only register of type dataType at address and placed at bitOffset in the word

    Create a read only register of type dataType at address and placed at bitOffset in the word

    Definition Classes
    BusSlaveFactory
  22. def createWriteAndReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

    Create multi-words write and read register of type dataType

    Create multi-words write and read register of type dataType

    Definition Classes
    BusSlaveFactory
  23. def createWriteMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

    Create multi-words write register of type dataType

    Create multi-words write register of type dataType

    Definition Classes
    BusSlaveFactory
  24. def createWriteOnly[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    Create a write only register of type dataType at address and placed at bitOffset in the word

    Create a write only register of type dataType at address and placed at bitOffset in the word

    Definition Classes
    BusSlaveFactory
  25. def dataModelString(): String
    Definition Classes
    BusSlaveFactoryDelayed
  26. def doBitsAccumulationAndClearOnRead(that: Bits, address: BigInt, bitOffset: Int = 0): Unit

    Instantiate an internal register which at each cycle do : reg := reg | that Then when a read occur, the register is cleared.

    Instantiate an internal register which at each cycle do : reg := reg | that Then when a read occur, the register is cleared. This register is readable at address and placed at bitOffset in the word

    Definition Classes
    BusSlaveFactory
  27. def doMappedElements(jobs: Seq[BusSlaveFactoryElement], askWrite: Bool, askRead: Bool, doWrite: Bool, doRead: Bool, writeData: Bits, readData: Bits): Unit
    Definition Classes
    BusSlaveFactoryDelayed
  28. def doMappedReadElements(jobs: Seq[BusSlaveFactoryElement], askRead: Bool, doRead: Bool, readData: Bits): Unit
    Definition Classes
    BusSlaveFactoryDelayed
  29. def doMappedWriteElements(jobs: Seq[BusSlaveFactoryElement], askWrite: Bool, doWrite: Bool, writeData: Bits): Unit
    Definition Classes
    BusSlaveFactoryDelayed
  30. def doNonStopWrite(writeData: Bits): Unit
    Definition Classes
    BusSlaveFactoryDelayed
  31. val doRead: Bool
  32. val doWrite: Bool
  33. def drive[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit
    Definition Classes
    BusSlaveFactory
  34. def drive[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    Drive that with a register writable at address placed at bitOffset in the word

    Drive that with a register writable at address placed at bitOffset in the word

    Definition Classes
    BusSlaveFactory
  35. def driveAndRead[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    Drive that with a register writable and readable at address placed at bitOffset in the word

    Drive that with a register writable and readable at address placed at bitOffset in the word

    Definition Classes
    BusSlaveFactory
  36. def driveAndReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

    Drive and read that on multi-word

    Drive and read that on multi-word

    Definition Classes
    BusSlaveFactory
  37. def driveFlow[T <: Data](that: Flow[T], address: BigInt, bitOffset: Int = 0, checkByteEnable: Boolean = false): Unit

    Emit on that a transaction when a write happen at address by using data placed at bitOffset in the word

    Emit on that a transaction when a write happen at address by using data placed at bitOffset in the word

    checkByteEnable

    do not trigger flow if byte enable is all zero. See https://github.com/SpinalHDL/SpinalHDL/issues/1265 for the discussion about this behaviour.

    Definition Classes
    BusSlaveFactory
  38. def driveMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

    Drive that on multi-words

    Drive that on multi-words

    Definition Classes
    BusSlaveFactory
  39. def driveStream[T <: Data](that: Stream[T], address: BigInt, bitOffset: Int = 0): Unit

    Emit on that a transaction when a write happen at address, by using data placed at bitOffset in the word.

    Emit on that a transaction when a write happen at address, by using data placed at bitOffset in the word. Block the write transaction until the transaction succeeds (stream becomes ready).

    Definition Classes
    BusSlaveFactory
  40. val elements: ArrayBuffer[BusSlaveFactoryElement]

    Contains all elements created

    Contains all elements created

    Definition Classes
    BusSlaveFactoryDelayed
  41. val elementsOk: HashSet[BusSlaveFactoryElement]
    Definition Classes
    BusSlaveFactoryDelayed
  42. val elementsPerAddress: LinkedHashMap[AddressMapping, ArrayBuffer[BusSlaveFactoryElement]]

    Contains all elements related to an address

    Contains all elements related to an address

    Definition Classes
    BusSlaveFactoryDelayed
  43. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  44. def equals(obj: Any): Boolean
    Definition Classes
    OverridedEqualsHashCode → AnyRef → Any
  45. def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit
    Definition Classes
    Nameable
  46. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  47. def getConfig: BusSlaveFactoryConfig
    Definition Classes
    BusSlaveFactory
  48. def getDisplayName(): String
    Definition Classes
    Nameable
  49. def getInstanceCounter: Int
    Definition Classes
    ContextUser
  50. def getMode: Byte
    Attributes
    protected
    Definition Classes
    Nameable
  51. def getName(default: String): String
    Definition Classes
    NameableByComponent → Nameable
  52. def getName(): String
    Definition Classes
    NameableByComponent → Nameable
  53. def getPartialName(): String
    Definition Classes
    Nameable
  54. def getPath(from: Component, to: Component): Seq[Component]
    Definition Classes
    NameableByComponent
  55. def getRefOwnersChain(): List[Any]
    Definition Classes
    OwnableRef
  56. def getScalaLocationLong: String
    Definition Classes
    ScalaLocated
  57. def getScalaLocationShort: String
    Definition Classes
    ScalaLocated
  58. def getScalaTrace(): Throwable
    Definition Classes
    ScalaLocated
  59. val globalData: GlobalData
    Definition Classes
    GlobalDataUser
  60. def hashCode(): Int
    Definition Classes
    OverridedEqualsHashCode → AnyRef → Any
  61. def isCompletelyUnnamed: Boolean
    Definition Classes
    Nameable
  62. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  63. final def isNamed: Boolean
    Definition Classes
    Nameable
  64. def isPriorityApplicable(namePriority: Byte): Boolean
    Definition Classes
    Nameable
  65. def isReading(address: BigInt): Bool

    Return true if the bus is reading

    Return true if the bus is reading

    Definition Classes
    BusSlaveFactory
  66. def isUnnamed: Boolean
    Definition Classes
    NameableByComponent → Nameable
  67. def isWriting(address: BigInt): Bool

    Return true if the bus is writing

    Return true if the bus is writing

    Definition Classes
    BusSlaveFactory
  68. def multiCycleRead(address: AddressMapping, cycles: BigInt): Unit
    Definition Classes
    BusSlaveFactory
  69. val name: String
    Definition Classes
    Nameable
  70. val nameableRef: Nameable
    Attributes
    protected
    Definition Classes
    Nameable
    Annotations
    @DontName()
  71. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  72. def nonStopWrite[T <: Data](that: T, bitOffset: Int = 0, documentation: String = null): T

    Permanently assign that by the bus write data from bitOffset

    Permanently assign that by the bus write data from bitOffset

    Definition Classes
    BusSlaveFactoryDelayed → BusSlaveFactory
  73. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  74. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  75. def onRead(address: BigInt, documentation: String = null)(doThat: ⇒ Unit): Unit

    Call doThat when a read transaction occurs on address

    Call doThat when a read transaction occurs on address

    Definition Classes
    BusSlaveFactory
  76. def onReadPrimitive(address: AddressMapping, haltSensitive: Boolean, documentation: String)(doThat: ⇒ Unit): Unit
    Definition Classes
    BusSlaveFactoryDelayed → BusSlaveFactory
  77. def onWrite(address: BigInt, documentation: String = null)(doThat: ⇒ Unit): Unit

    Call doThat when a write transaction occurs on address

    Call doThat when a write transaction occurs on address

    Definition Classes
    BusSlaveFactory
  78. def onWritePrimitive(address: AddressMapping, haltSensitive: Boolean, documentation: String)(doThat: ⇒ Unit): Unit
    Definition Classes
    BusSlaveFactoryDelayed → BusSlaveFactory
  79. def overrideLocalName(name: String): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  80. val parentScope: ScopeStatement
    Definition Classes
    ContextUser
  81. def printDataModel(): Unit
    Definition Classes
    BusSlaveFactoryDelayed
  82. def read[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit
    Definition Classes
    BusSlaveFactory
  83. def read[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    When the bus read the address, fill the response with that at bitOffset

    When the bus read the address, fill the response with that at bitOffset

    Definition Classes
    BusSlaveFactory
  84. def readAddress(): UInt
    Definition Classes
    WishboneSlaveFactory → BusSlaveFactory
  85. def readAddress(address: AddressMapping): UInt
    Definition Classes
    BusSlaveFactory
  86. def readAndClearOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
    Definition Classes
    BusSlaveFactory
  87. def readAndSetOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
    Definition Classes
    BusSlaveFactory
  88. def readAndWrite(that: Data, address: BigInt, bitOffset: Int = 0, documentation: String = null): Unit

    Make that readable and writable at address and placed at bitOffset in the word

    Make that readable and writable at address and placed at bitOffset in the word

    Definition Classes
    BusSlaveFactory
  89. def readAndWriteMultiWord(that: Data, address: BigInt, documentation: String = null): Unit

    Create the memory mapping to write/read that from address

    Create the memory mapping to write/read that from address

    Definition Classes
    BusSlaveFactory
  90. def readError(): Unit
    Definition Classes
    BusSlaveFactory
  91. val readErrorFlag: Bool
    Definition Classes
    BusSlaveFactory
  92. def readFire(): Bool
    Definition Classes
    BusSlaveFactory
  93. def readHalt(): Unit
    Definition Classes
    WishboneSlaveFactory → BusSlaveFactory
  94. def readMultiWord(that: Data, address: BigInt, documentation: String = null): Unit

    Create the memory mapping to read that from address If that is bigger than one word it extends the register on following addresses.

    Create the memory mapping to read that from address If that is bigger than one word it extends the register on following addresses.

    Definition Classes
    BusSlaveFactory
  95. def readPrimitive[T <: Data](that: T, address: AddressMapping, bitOffset: Int, documentation: String): Unit
    Definition Classes
    BusSlaveFactoryDelayed → BusSlaveFactory
  96. def readStreamBlockCycles[T <: Data](that: Stream[T], address: BigInt, blockCycles: UInt, timeout: Bool = null): Unit

    Same as readStreamNonBlocking, but block the bus for at most blockCycles before returning the NACK.

    Same as readStreamNonBlocking, but block the bus for at most blockCycles before returning the NACK.

    T

    type of stream payload

    that

    data to read over bus

    address

    address to map at

    blockCycles

    cycles to block read transaction before returning NACK

    timeout

    whether the read transaction timed out (returned NACK)

    Definition Classes
    BusSlaveFactory
  97. def readStreamNonBlocking[T <: Data](that: Stream[T], address: BigInt, validBitOffset: Int, payloadBitOffset: Int, validInverted: Boolean = false): Unit

    Read that and consume the transaction when a read happen at address.

    Read that and consume the transaction when a read happen at address.

    Definition Classes
    BusSlaveFactory
  98. def readStreamNonBlocking[T <: Data](that: Stream[T], address: BigInt): Unit

    Read that (that is bigger than the busWidth) and consume the transaction when a read happen at address.

    Read that (that is bigger than the busWidth) and consume the transaction when a read happen at address.

    Definition Classes
    BusSlaveFactory
    Note

    in order to avoid to read wrong data read first the address which contains the valid signal. Little : payload - valid at address 0x00 Big : valid - payload at address 0x00 Once the valid signal is true you can read all registers

  99. def readSyncMemMultiWord[T <: Data](mem: Mem[T], addressOffset: BigInt, memOffset: UInt = U(0).resized): Mem[T]

    Memory map a Mem to bus for reading.

    Memory map a Mem to bus for reading. Elements can be larger than bus data width in bits.

    Definition Classes
    BusSlaveFactory
  100. def readSyncMemWordAligned[T <: Data](mem: Mem[T], addressOffset: BigInt, bitOffset: Int = 0, memOffset: UInt = U(0).resized): Mem[T]
    Definition Classes
    BusSlaveFactory
  101. val refOwner: RefOwnerType
    Definition Classes
    OwnableRef
    Annotations
    @DontName()
  102. def reflectNames(): Unit
    Definition Classes
    Nameable
  103. def rework[T](body: ⇒ T): T
    Definition Classes
    Area
  104. val scalaTrace: Throwable
    Definition Classes
    ScalaLocated
  105. def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  106. def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  107. def setCompositeName(nameable: Nameable, postfix: String): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  108. def setCompositeName(nameable: Nameable, namePriority: Byte): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  109. def setCompositeName(nameable: Nameable, weak: Boolean): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  110. def setCompositeName(nameable: Nameable): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  111. def setConfig(value: BusSlaveFactoryConfig): WishboneSlaveFactory.this.type
    Definition Classes
    BusSlaveFactory
  112. def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  113. def setName(name: String, namePriority: Byte): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  114. def setName(name: String, weak: Boolean): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  115. def setName(name: String): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  116. def setNameAsWeak(): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  117. def setOnClear[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
    Definition Classes
    BusSlaveFactory
  118. def setOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
    Definition Classes
    BusSlaveFactory
  119. def setPartialName(name: String, namePriority: Byte, owner: Any): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  120. def setPartialName(name: String, namePriority: Byte): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  121. def setPartialName(name: String, weak: Boolean): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  122. def setPartialName(owner: Nameable, name: String, namePriority: Byte): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  123. def setPartialName(owner: Nameable, name: String, weak: Boolean): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  124. def setPartialName(name: String): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  125. def setPartialName(owner: Nameable, name: String): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  126. def setPartialName(owner: Nameable): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  127. def setRefOwner(that: Any): Unit
    Definition Classes
    OwnableRef
  128. def setScalaLocated(source: ScalaLocated): WishboneSlaveFactory.this.type
    Definition Classes
    ScalaLocated
  129. def setWeakName(name: String): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  130. def setWordEndianness(value: Endianness): BusSlaveFactory

    Set the endianness during write/read multiword

    Set the endianness during write/read multiword

    Definition Classes
    BusSlaveFactory
  131. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  132. def toString(): String
    Definition Classes
    Area → Nameable → AnyRef → Any
  133. def unsetName(): WishboneSlaveFactory.this.type
    Definition Classes
    Nameable
  134. def valCallback[T](ref: T, name: String): T
    Definition Classes
    ValCallbackRec → ValCallback
  135. def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit
    Definition Classes
    ValCallbackRec
  136. def valCallbackRec(obj: Any, name: String): Unit
    Definition Classes
    Area → ValCallbackRec
  137. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  138. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  139. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  140. def withOffset(offset: BigInt): BusSlaveFactoryAddressWrapper
    Definition Classes
    BusSlaveFactory
  141. def wordAddressInc: Int

    Address incrementation used by the read and write multi words registers

    Address incrementation used by the read and write multi words registers

    Definition Classes
    BusSlaveFactory
  142. def write[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit
    Definition Classes
    BusSlaveFactory
  143. def write[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    When the bus write the address, assign that with bus’s data from bitOffset

    When the bus write the address, assign that with bus’s data from bitOffset

    Definition Classes
    BusSlaveFactory
  144. def writeAddress(): UInt
    Definition Classes
    WishboneSlaveFactory → BusSlaveFactory
  145. def writeAddress(address: AddressMapping): UInt
    Definition Classes
    BusSlaveFactory
  146. def writeByteEnable(): Bits

    Byte enable bits, defaulting to all ones

    Byte enable bits, defaulting to all ones

    Definition Classes
    WishboneSlaveFactory → BusSlaveFactory
  147. def writeError(): Unit
    Definition Classes
    BusSlaveFactory
  148. val writeErrorFlag: Bool
    Definition Classes
    BusSlaveFactory
  149. def writeFire(): Bool
    Definition Classes
    BusSlaveFactory
  150. def writeHalt(): Unit
    Definition Classes
    WishboneSlaveFactory → BusSlaveFactory
  151. def writeMemMultiWord[T <: Data](mem: Mem[T], addressOffset: BigInt): Mem[T]

    Memory map a Mem to bus for writing.

    Memory map a Mem to bus for writing. Elements can be larger than bus data width in bits.

    Definition Classes
    BusSlaveFactory
  152. def writeMemWordAligned[T <: Data](mem: Mem[T], addressOffset: BigInt, bitOffset: Int = 0, memOffset: UInt = U(0).resized): Mem[T]
    Definition Classes
    BusSlaveFactory
  153. def writeMultiWord(that: Data, address: BigInt, documentation: String = null): Unit

    Create the memory mapping to write that at address.

    Create the memory mapping to write that at address. If that is bigger than one word it extends the register on following addresses.

    Definition Classes
    BusSlaveFactory
  154. def writePrimitive[T <: Data](that: T, address: AddressMapping, bitOffset: Int, documentation: String): Unit
    Definition Classes
    BusSlaveFactoryDelayed → BusSlaveFactory

Deprecated Value Members

  1. def createReadWrite[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T
    Definition Classes
    BusSlaveFactory
    Annotations
    @deprecated
    Deprecated

    (Since version ???) Use createReadAndWrite instead

  2. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from BusSlaveFactoryDelayed

Inherited from BusSlaveFactory

Inherited from Area

Inherited from OverridedEqualsHashCode

Inherited from ValCallbackRec

Inherited from ValCallback

Inherited from NameableByComponent

Inherited from Nameable

Inherited from ContextUser

Inherited from ScalaLocated

Inherited from GlobalDataUser

Inherited from OwnableRef

Inherited from AnyRef

Inherited from Any

Ungrouped