t

spinal.lib.bus.misc

BusSlaveFactory

trait BusSlaveFactory extends Area

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  1. BusSlaveFactory
  2. Area
  3. OverridedEqualsHashCode
  4. ValCallbackRec
  5. ValCallback
  6. NameableByComponent
  7. Nameable
  8. ContextUser
  9. ScalaLocated
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Type Members

  1. abstract type RefOwnerType
    Definition Classes
    OwnableRef

Abstract Value Members

  1. abstract def busDataWidth: Int

    Return the data width of the bus

  2. abstract def nonStopWrite[T <: Data](that: T, bitOffset: Int = 0, documentation: String = null): T

    Permanently assign that by the bus write data from bitOffset

  3. abstract def onReadPrimitive(address: AddressMapping, haltSensitive: Boolean, documentation: String)(doThat: ⇒ Unit): Unit
  4. abstract def onWritePrimitive(address: AddressMapping, haltSensitive: Boolean, documentation: String)(doThat: ⇒ Unit): Unit
  5. abstract def readAddress(): UInt
  6. abstract def readHalt(): Unit
  7. abstract def readPrimitive[T <: Data](that: T, address: AddressMapping, bitOffset: Int, documentation: String): Unit
  8. abstract def writeAddress(): UInt
  9. abstract def writeHalt(): Unit
  10. abstract def writePrimitive[T <: Data](that: T, address: AddressMapping, bitOffset: Int, documentation: String): Unit

Concrete Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. val _config: BusSlaveFactoryConfig

    Configuration of the BusSlaveFactory

    Configuration of the BusSlaveFactory

    Attributes
    protected
  5. val _context: Capture
    Definition Classes
    Area
  6. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  7. def childNamePriority: Byte
    Definition Classes
    Area
  8. def clearOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
  9. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @IntrinsicCandidate()
  10. def component: Component
    Definition Classes
    ContextUser
  11. def createAndDriveFlow[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, checkByteEnable: Boolean = false): Flow[T]

    Create a writable Flow register of type dataType at address and placed at bitOffset in the word

    Create a writable Flow register of type dataType at address and placed at bitOffset in the word

    checkByteEnable

    do not trigger flow if byte enable is all zero. See https://github.com/SpinalHDL/SpinalHDL/issues/1265 for the discussion about this behaviour.

  12. def createReadAndClearOnSet[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T
  13. def createReadAndSetOnSet[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T
  14. def createReadAndWrite[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    Create a read write register of type dataType at address and placed at bitOffset in the word

  15. def createReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

    Create multi-words read register of type dataType

  16. def createReadOnly[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    Create a read only register of type dataType at address and placed at bitOffset in the word

  17. def createWriteAndReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

    Create multi-words write and read register of type dataType

  18. def createWriteMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

    Create multi-words write register of type dataType

  19. def createWriteOnly[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    Create a write only register of type dataType at address and placed at bitOffset in the word

  20. def doBitsAccumulationAndClearOnRead(that: Bits, address: BigInt, bitOffset: Int = 0): Unit

    Instantiate an internal register which at each cycle do : reg := reg | that Then when a read occur, the register is cleared.

    Instantiate an internal register which at each cycle do : reg := reg | that Then when a read occur, the register is cleared. This register is readable at address and placed at bitOffset in the word

  21. def drive[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit
  22. def drive[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    Drive that with a register writable at address placed at bitOffset in the word

  23. def driveAndRead[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    Drive that with a register writable and readable at address placed at bitOffset in the word

  24. def driveAndReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

    Drive and read that on multi-word

  25. def driveFlow[T <: Data](that: Flow[T], address: BigInt, bitOffset: Int = 0, checkByteEnable: Boolean = false): Unit

    Emit on that a transaction when a write happen at address by using data placed at bitOffset in the word

    Emit on that a transaction when a write happen at address by using data placed at bitOffset in the word

    checkByteEnable

    do not trigger flow if byte enable is all zero. See https://github.com/SpinalHDL/SpinalHDL/issues/1265 for the discussion about this behaviour.

  26. def driveMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T

    Drive that on multi-words

  27. def driveStream[T <: Data](that: Stream[T], address: BigInt, bitOffset: Int = 0): Unit

    Emit on that a transaction when a write happen at address, by using data placed at bitOffset in the word.

    Emit on that a transaction when a write happen at address, by using data placed at bitOffset in the word. Block the write transaction until the transaction succeeds (stream becomes ready).

  28. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  29. def equals(obj: Any): Boolean
    Definition Classes
    OverridedEqualsHashCode → AnyRef → Any
  30. def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit
    Definition Classes
    Nameable
  31. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  32. def getConfig: BusSlaveFactoryConfig
  33. def getDisplayName(): String
    Definition Classes
    Nameable
  34. def getInstanceCounter: Int
    Definition Classes
    ContextUser
  35. def getMode: Byte
    Attributes
    protected
    Definition Classes
    Nameable
  36. def getName(default: String): String
    Definition Classes
    NameableByComponent → Nameable
  37. def getName(): String
    Definition Classes
    NameableByComponent → Nameable
  38. def getPartialName(): String
    Definition Classes
    Nameable
  39. def getPath(from: Component, to: Component): Seq[Component]
    Definition Classes
    NameableByComponent
  40. def getRefOwnersChain(): List[Any]
    Definition Classes
    OwnableRef
  41. def getScalaLocationLong: String
    Definition Classes
    ScalaLocated
  42. def getScalaLocationShort: String
    Definition Classes
    ScalaLocated
  43. def getScalaTrace(): Throwable
    Definition Classes
    ScalaLocated
  44. val globalData: GlobalData
    Definition Classes
    GlobalDataUser
  45. def hashCode(): Int
    Definition Classes
    OverridedEqualsHashCode → AnyRef → Any
  46. def isCompletelyUnnamed: Boolean
    Definition Classes
    Nameable
  47. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  48. final def isNamed: Boolean
    Definition Classes
    Nameable
  49. def isPriorityApplicable(namePriority: Byte): Boolean
    Definition Classes
    Nameable
  50. def isReading(address: BigInt): Bool

    Return true if the bus is reading

  51. def isUnnamed: Boolean
    Definition Classes
    NameableByComponent → Nameable
  52. def isWriting(address: BigInt): Bool

    Return true if the bus is writing

  53. def multiCycleRead(address: AddressMapping, cycles: BigInt): Unit
  54. val name: String
    Definition Classes
    Nameable
  55. val nameableRef: Nameable
    Attributes
    protected
    Definition Classes
    Nameable
    Annotations
    @DontName()
  56. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  57. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  58. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  59. def onRead(address: BigInt, documentation: String = null)(doThat: ⇒ Unit): Unit

    Call doThat when a read transaction occurs on address

  60. def onWrite(address: BigInt, documentation: String = null)(doThat: ⇒ Unit): Unit

    Call doThat when a write transaction occurs on address

  61. def overrideLocalName(name: String): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  62. val parentScope: ScopeStatement
    Definition Classes
    ContextUser
  63. def read[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit
  64. def read[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    When the bus read the address, fill the response with that at bitOffset

  65. def readAddress(address: AddressMapping): UInt
  66. def readAndClearOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
  67. def readAndSetOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
  68. def readAndWrite(that: Data, address: BigInt, bitOffset: Int = 0, documentation: String = null): Unit

    Make that readable and writable at address and placed at bitOffset in the word

  69. def readAndWriteMultiWord(that: Data, address: BigInt, documentation: String = null): Unit

    Create the memory mapping to write/read that from address

  70. def readError(): Unit
  71. val readErrorFlag: Bool
  72. def readFire(): Bool
  73. def readMultiWord(that: Data, address: BigInt, documentation: String = null): Unit

    Create the memory mapping to read that from address If that is bigger than one word it extends the register on following addresses.

  74. def readStreamBlockCycles[T <: Data](that: Stream[T], address: BigInt, blockCycles: UInt, timeout: Bool = null): Unit

    Same as readStreamNonBlocking, but block the bus for at most blockCycles before returning the NACK.

    Same as readStreamNonBlocking, but block the bus for at most blockCycles before returning the NACK.

    T

    type of stream payload

    that

    data to read over bus

    address

    address to map at

    blockCycles

    cycles to block read transaction before returning NACK

    timeout

    whether the read transaction timed out (returned NACK)

  75. def readStreamNonBlocking[T <: Data](that: Stream[T], address: BigInt, validBitOffset: Int, payloadBitOffset: Int, validInverted: Boolean = false): Unit

    Read that and consume the transaction when a read happen at address.

  76. def readStreamNonBlocking[T <: Data](that: Stream[T], address: BigInt): Unit

    Read that (that is bigger than the busWidth) and consume the transaction when a read happen at address.

    Read that (that is bigger than the busWidth) and consume the transaction when a read happen at address.

    Note

    in order to avoid to read wrong data read first the address which contains the valid signal. Little : payload - valid at address 0x00 Big : valid - payload at address 0x00 Once the valid signal is true you can read all registers

  77. def readSyncMemMultiWord[T <: Data](mem: Mem[T], addressOffset: BigInt, memOffset: UInt = U(0).resized): Mem[T]

    Memory map a Mem to bus for reading.

    Memory map a Mem to bus for reading. Elements can be larger than bus data width in bits.

  78. def readSyncMemWordAligned[T <: Data](mem: Mem[T], addressOffset: BigInt, bitOffset: Int = 0, memOffset: UInt = U(0).resized): Mem[T]
  79. val refOwner: RefOwnerType
    Definition Classes
    OwnableRef
    Annotations
    @DontName()
  80. def reflectNames(): Unit
    Definition Classes
    Nameable
  81. def rework[T](body: ⇒ T): T
    Definition Classes
    Area
  82. val scalaTrace: Throwable
    Definition Classes
    ScalaLocated
  83. def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  84. def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  85. def setCompositeName(nameable: Nameable, postfix: String): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  86. def setCompositeName(nameable: Nameable, namePriority: Byte): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  87. def setCompositeName(nameable: Nameable, weak: Boolean): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  88. def setCompositeName(nameable: Nameable): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  89. def setConfig(value: BusSlaveFactoryConfig): BusSlaveFactory.this.type
  90. def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  91. def setName(name: String, namePriority: Byte): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  92. def setName(name: String, weak: Boolean): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  93. def setName(name: String): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  94. def setNameAsWeak(): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  95. def setOnClear[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
  96. def setOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
  97. def setPartialName(name: String, namePriority: Byte, owner: Any): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  98. def setPartialName(name: String, namePriority: Byte): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  99. def setPartialName(name: String, weak: Boolean): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  100. def setPartialName(owner: Nameable, name: String, namePriority: Byte): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  101. def setPartialName(owner: Nameable, name: String, weak: Boolean): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  102. def setPartialName(name: String): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  103. def setPartialName(owner: Nameable, name: String): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  104. def setPartialName(owner: Nameable): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  105. def setRefOwner(that: Any): Unit
    Definition Classes
    OwnableRef
  106. def setScalaLocated(source: ScalaLocated): BusSlaveFactory.this.type
    Definition Classes
    ScalaLocated
  107. def setWeakName(name: String): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  108. def setWordEndianness(value: Endianness): BusSlaveFactory

    Set the endianness during write/read multiword

  109. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  110. def toString(): String
    Definition Classes
    Area → Nameable → AnyRef → Any
  111. def unsetName(): BusSlaveFactory.this.type
    Definition Classes
    Nameable
  112. def valCallback[T](ref: T, name: String): T
    Definition Classes
    ValCallbackRec → ValCallback
  113. def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit
    Definition Classes
    ValCallbackRec
  114. def valCallbackRec(obj: Any, name: String): Unit
    Definition Classes
    Area → ValCallbackRec
  115. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  116. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  117. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  118. def withOffset(offset: BigInt): BusSlaveFactoryAddressWrapper
  119. def wordAddressInc: Int

    Address incrementation used by the read and write multi words registers

  120. def write[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit
  121. def write[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T

    When the bus write the address, assign that with bus’s data from bitOffset

  122. def writeAddress(address: AddressMapping): UInt
  123. def writeByteEnable(): Bits

    Byte enable bits, defaulting to all ones

  124. def writeError(): Unit
  125. val writeErrorFlag: Bool
  126. def writeFire(): Bool
  127. def writeMemMultiWord[T <: Data](mem: Mem[T], addressOffset: BigInt): Mem[T]

    Memory map a Mem to bus for writing.

    Memory map a Mem to bus for writing. Elements can be larger than bus data width in bits.

  128. def writeMemWordAligned[T <: Data](mem: Mem[T], addressOffset: BigInt, bitOffset: Int = 0, memOffset: UInt = U(0).resized): Mem[T]
  129. def writeMultiWord(that: Data, address: BigInt, documentation: String = null): Unit

    Create the memory mapping to write that at address.

    Create the memory mapping to write that at address. If that is bigger than one word it extends the register on following addresses.

Deprecated Value Members

  1. def createReadWrite[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T
    Annotations
    @deprecated
    Deprecated

    (Since version ???) Use createReadAndWrite instead

  2. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from Area

Inherited from OverridedEqualsHashCode

Inherited from ValCallbackRec

Inherited from ValCallback

Inherited from NameableByComponent

Inherited from Nameable

Inherited from ContextUser

Inherited from ScalaLocated

Inherited from GlobalDataUser

Inherited from OwnableRef

Inherited from AnyRef

Inherited from Any

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