Packages

case class MemBus(c: MemBusConfig) extends Interface with IMasterSlave with Product with Serializable

Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. MemBus
  2. Serializable
  3. Serializable
  4. Product
  5. Equals
  6. IMasterSlave
  7. Interface
  8. Bundle
  9. ValCallbackRec
  10. ValCallback
  11. MultiData
  12. Data
  13. InComponent
  14. OverridedEqualsHashCode
  15. SpinalTagReady
  16. Assignable
  17. NameableByComponent
  18. Nameable
  19. OwnableRef
  20. ContextUser
  21. ScalaLocated
  22. GlobalDataUser
  23. AnyRef
  24. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Instance Constructors

  1. new MemBus(c: MemBusConfig)

Type Members

  1. abstract type RefOwnerType
    Definition Classes
    OwnableRef

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. def ##(right: Data): Bits

    Concatenation between two signals

    Concatenation between two signals

    Definition Classes
    Data
  3. final def ##(): Int
    Definition Classes
    AnyRef → Any
  4. def #*(count: Int): Bits

    Return the count time concatenation of the signal.

    Return the count time concatenation of the signal.

    Definition Classes
    Data
  5. def <<(that: MemBus): Unit
  6. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  7. def >>(that: MemBus): Unit
  8. val IFGeneric: LinkedHashMap[(Data, String), String]
    Definition Classes
    Interface
  9. def IFparent: Data
    Definition Classes
    Data
  10. val _spinalTags: LinkedHashSet[SpinalTag]
    Definition Classes
    SpinalTagReady
  11. def addAttribute(attribute: Attribute): MemBus.this.type
    Definition Classes
    Data → SpinalTagReady
  12. def addAttribute(name: String, value: Int): MemBus.this.type
    Definition Classes
    SpinalTagReady
  13. def addAttribute(name: String, value: String): MemBus.this.type
    Definition Classes
    SpinalTagReady
  14. def addAttribute(name: String): MemBus.this.type
    Definition Classes
    SpinalTagReady
  15. def addGeneric(name: String, that: Any, default: String = null): String
    Definition Classes
    Interface
  16. def addParameter(name: String, that: Any, default: String = null): String
    Definition Classes
    Interface
  17. def addTag[T <: SpinalTag](spinalTag: T): MemBus.this.type
    Definition Classes
    MultiData → SpinalTagReady
  18. def addTags(h: SpinalTag, tail: SpinalTag*): MemBus.this.type
    Definition Classes
    SpinalTagReady
  19. def addTags[T <: SpinalTag](tags: Iterable[T]): MemBus.this.type
    Definition Classes
    SpinalTagReady
  20. val addr: UInt
  21. def allModPort: List[String]
    Definition Classes
    Interface
  22. def allowDirectionLessIo(): MemBus.this.type

    Allow a signal of an io Bundle to be directionless.

    Allow a signal of an io Bundle to be directionless.

    Definition Classes
    Data
    See also

    IO Bundle Error Documentation

  23. def allowOverride(): MemBus.this.type

    Allow a signal to be overridden.

    Allow a signal to be overridden.

    Definition Classes
    Data
    See also

    Assignment overlap Error Documentation

  24. def allowPartialyAssigned(): MemBus.this.type

    Allow a register to be partially assigned

    Allow a register to be partially assigned

    Definition Classes
    Data
  25. def allowPruning(): MemBus.this.type
    Definition Classes
    Data
  26. def allowSimplifyIt(): MemBus.this.type
    Definition Classes
    Data
  27. def allowUnsetRegToAvoidLatch(): MemBus.this.type

    Allow a register to have only an init (no assignments)

    Allow a register to have only an init (no assignments)

    Definition Classes
    Data
    See also

    "Register with only init" Error Documentation

  28. def as[T <: Data](dataType: HardType[T]): T
    Definition Classes
    Data
  29. def asBits: Bits

    Cast signal to Bits

    Cast signal to Bits

    Definition Classes
    MultiData → Data
  30. def asData: Data
    Definition Classes
    Data
  31. def asInOut(): MemBus.this.type

    Set a signal as inout

    Set a signal as inout

    Definition Classes
    MultiData → Data
  32. def asInput(): MemBus.this.type

    Set a data as input

    Set a data as input

    Definition Classes
    MultiData → Data
  33. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  34. def asOutput(): MemBus.this.type

    Set a data as output

    Set a data as output

    Definition Classes
    MultiData → Data
  35. def assignAllByName(that: Bundle): Unit

    Assign the bundle with an other bundle by name

    Assign the bundle with an other bundle by name

    Definition Classes
    Bundle
  36. def assignDontCare(): MemBus.this.type

    Assign the default 'x' value to all signals composing this type.

    Assign the default 'x' value to all signals composing this type.

    Definition Classes
    Data
    See also

    Data type documentation

    "Don't care term" wikipedia article

  37. def assignDontCareToUnasigned(): MemBus.this.type
    Definition Classes
    Data
  38. def assignFormalRandom(kind: RandomExpKind): Unit
    Definition Classes
    MultiData → Data
  39. final def assignFrom(that: AnyRef, target: AnyRef = this)(implicit loc: Location): Unit
    Definition Classes
    Data
  40. def assignFromBits(bits: Bits, hi: Int, lo: Int): Unit
    Definition Classes
    MultiData → Data
  41. def assignFromBits(bits: Bits): Unit
    Definition Classes
    MultiData → Data
  42. def assignFromBits(bits: Bits, offset: Int, bitCount: BitCount): Unit
    Definition Classes
    Data
  43. def assignFromImpl(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit
    Attributes
    protected
    Definition Classes
    Bundle → Assignable
  44. def assignSomeByName(that: Bundle): Unit

    Assign all possible signal fo the bundle with an other bundle by name

    Assign all possible signal fo the bundle with an other bundle by name

    Definition Classes
    Bundle
  45. def assignUnassignedByName(that: MultiData): Unit
    Definition Classes
    MultiData
  46. def bundleAssign(that: Bundle)(f: (Data, Data) ⇒ Unit): Unit
    Definition Classes
    Bundle
  47. val c: MemBusConfig
  48. def callModPort(s: String): Unit
    Definition Classes
    Interface
  49. val ce: Bool
  50. def checkDir(that: Bundle): Boolean

    for interface find modport

    for interface find modport

    Definition Classes
    Bundle
  51. def checkModport(): List[String]
    Definition Classes
    Interface
  52. def clearAll(): MemBus.this.type

    Clear all bits to False and return itself

    Clear all bits to False and return itself

    Definition Classes
    Data
  53. def clone(): Interface
    Definition Classes
    Interface → Bundle → Data → AnyRef
  54. def component: Component
    Definition Classes
    ContextUser
  55. final def compositAssignFrom(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit
    Definition Classes
    Assignable
  56. val compositeAssign: Assignable
    Definition Classes
    Assignable
  57. def copyDirectionOfImpl(that: Data): MemBus.this.type
    Definition Classes
    MultiData → Data
  58. var definitionName: String
    Definition Classes
    Interface
  59. def dirString(): String
    Definition Classes
    Data
  60. def dontSimplifyIt(): MemBus.this.type
    Definition Classes
    Data
  61. def elements: ArrayBuffer[(String, Data)]
    Definition Classes
    Bundle → MultiData
  62. var elementsCache: ArrayBuffer[(String, Data)]
    Definition Classes
    Bundle
  63. def elementsString: String
    Definition Classes
    MultiData
  64. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  65. def equals(obj: Any): Boolean
    Definition Classes
    OverridedEqualsHashCode → AnyRef → Any
  66. def existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean
    Definition Classes
    SpinalTagReady
  67. def filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]
    Definition Classes
    SpinalTagReady
  68. def find(name: String): Data
    Definition Classes
    MultiData
  69. def findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]
    Definition Classes
    SpinalTagReady
  70. def flatten: Seq[BaseType]
    Definition Classes
    MultiData → Data
  71. def flattenForeach(body: (BaseType) ⇒ Unit): Unit
    Definition Classes
    MultiData → Data
  72. def flattenLocalName: Seq[String]
    Definition Classes
    MultiData → Data
  73. def flip(): MemBus.this.type

    Flip the direction of the signal.

    Flip the direction of the signal.

    in and out are swapped, inout stay the same.

    Definition Classes
    MultiData → Data
  74. def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit
    Definition Classes
    Nameable
  75. def foreachTag(body: (SpinalTag) ⇒ Unit): Unit
    Definition Classes
    SpinalTagReady
  76. def freeze(): MemBus.this.type
    Definition Classes
    MultiData → Data
  77. val genericElements: ArrayBuffer[(String, Any, String)]
    Definition Classes
    Interface
  78. def getAheadValue(): MemBus.this.type

    For a register, get the value it will have at the next clock, as a combinational signal.

    For a register, get the value it will have at the next clock, as a combinational signal.

    Definition Classes
    Data
  79. def getBitsWidth: Int

    Return the width of the data

    Return the width of the data

    Definition Classes
    MultiData → Data
  80. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  81. def getComponent(): Component
    Definition Classes
    Data → InComponent → NameableByComponent
  82. def getComponents(): Seq[Component]

    Get current component with all parents

    Get current component with all parents

    Definition Classes
    InComponent
  83. def getDirection: IODirection
    Definition Classes
    Data
  84. def getDisplayName(): String
    Definition Classes
    Nameable
  85. def getInstanceCounter: Int
    Definition Classes
    ContextUser
  86. def getMode: Byte
    Attributes
    protected
    Definition Classes
    Nameable
  87. def getMuxType[T <: Data](list: TraversableOnce[T]): HardType[T]
    Definition Classes
    Data
  88. def getName(default: String): String
    Definition Classes
    NameableByComponent → Nameable
  89. def getName(): String
    Definition Classes
    NameableByComponent → Nameable
  90. def getPartialName(): String
    Definition Classes
    Nameable
  91. def getPath(from: Component, to: Component): Seq[Component]
    Definition Classes
    NameableByComponent
  92. def getRealSource: Any
    Definition Classes
    Assignable
  93. def getRealSourceNoRec: Any
    Definition Classes
    Data → Assignable
  94. def getRefOwnersChain(): List[Any]
    Definition Classes
    OwnableRef
  95. def getRootParent: Data
    Definition Classes
    Data
  96. def getRtlPath(separator: String = "/"): String
    Definition Classes
    Data
  97. def getScalaLocationLong: String
    Definition Classes
    ScalaLocated
  98. def getScalaLocationShort: String
    Definition Classes
    ScalaLocated
  99. def getScalaTrace(): Throwable
    Definition Classes
    ScalaLocated
  100. def getTag[T <: SpinalTag](clazz: Class[T]): Option[T]
    Definition Classes
    SpinalTagReady
  101. def getTags(): LinkedHashSet[SpinalTag]
    Definition Classes
    SpinalTagReady
  102. def getTagsOf[T <: SpinalTag]()(implicit tag: ClassTag[T]): Iterable[T]
    Definition Classes
    SpinalTagReady
  103. def getTypeString: String
    Definition Classes
    Bundle
  104. def getZero: MemBus.this.type

    Create a signal set to 0

    Create a signal set to 0

    Definition Classes
    MultiData → Data
  105. val globalData: GlobalData
    Definition Classes
    GlobalDataUser
  106. var hardtype: HardType[_]
    Definition Classes
    Bundle
  107. def hasTag[T <: SpinalTag](clazz: Class[T]): Boolean
    Definition Classes
    SpinalTagReady
  108. def hasTag(spinalTag: SpinalTag): Boolean
    Definition Classes
    SpinalTagReady
  109. def hashCode(): Int
    Definition Classes
    OverridedEqualsHashCode → AnyRef → Any
  110. final def initFrom(that: AnyRef, target: AnyRef = this): Unit
    Definition Classes
    Data
  111. def instanceAttributes(language: Language): Iterable[Attribute]
    Definition Classes
    SpinalTagReady
  112. def instanceAttributes: Iterable[Attribute]
    Definition Classes
    SpinalTagReady
  113. final def intoMaster(): MemBus.this.type

    Convert into master

    Convert into master

    Definition Classes
    IMasterSlave
  114. final def intoSlave(): MemBus.this.type

    Convert into slave

    Convert into slave

    Definition Classes
    IMasterSlave
  115. def isAnalog: Boolean
    Definition Classes
    Data
  116. def isComb: Boolean
    Definition Classes
    Data
  117. def isCompletelyUnnamed: Boolean
    Definition Classes
    Nameable
  118. def isDirectionLess: Boolean
    Definition Classes
    Data
  119. def isEmptyOfTag: Boolean
    Definition Classes
    SpinalTagReady
  120. def isInOut: Boolean
    Definition Classes
    Data
  121. def isInput: Boolean
    Definition Classes
    Data
  122. def isInputOrInOut: Boolean
    Definition Classes
    Data
  123. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  124. final def isMasterInterface: Boolean

    Are port directions set for a Master interface?

    Are port directions set for a Master interface?

    Definition Classes
    IMasterSlave
  125. final def isNamed: Boolean
    Definition Classes
    Nameable
  126. def isOutput: Boolean
    Definition Classes
    Data
  127. def isOutputOrInOut: Boolean
    Definition Classes
    Data
  128. def isPriorityApplicable(namePriority: Byte): Boolean
    Definition Classes
    Nameable
  129. def isReg: Boolean
    Definition Classes
    Data
  130. def isRegOnAssign: Boolean
    Definition Classes
    Data
  131. final def isSlaveInterface: Boolean

    Are port directions set for a Master interface?

    Are port directions set for a Master interface?

    Definition Classes
    IMasterSlave
  132. def isUnnamed: Boolean
    Definition Classes
    NameableByComponent → Nameable
  133. def mst: Unit
    Annotations
    @modport()
  134. val name: String
    Definition Classes
    Nameable
  135. val nameableRef: Nameable
    Attributes
    protected
    Definition Classes
    Nameable
    Annotations
    @DontName()
  136. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  137. def noBackendCombMerge(): MemBus.this.type

    Put the combinatorial logic driving this signal in a separate process

    Put the combinatorial logic driving this signal in a separate process

    Definition Classes
    Data
  138. def noCombLoopCheck(): MemBus.this.type

    Disable combinatorial loop checking for this Data

    Disable combinatorial loop checking for this Data

    Definition Classes
    Data
    See also

    Combinatorial loop Error Documentation

  139. def notSVIF(): Unit
    Definition Classes
    Interface
  140. def notSVIFthisLevel(): Unit
    Definition Classes
    Interface
  141. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  142. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  143. def onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit
    Definition Classes
    SpinalTagReady
  144. def overrideLocalName(name: String): MemBus.this.type
    Definition Classes
    Nameable
  145. val parent: Data
    Definition Classes
    Data
  146. val parentScope: ScopeStatement
    Definition Classes
    ContextUser
  147. def pull(propagateName: Boolean): MemBus.this.type
    Definition Classes
    Data
  148. def pull(): MemBus.this.type

    Pull a signal to the top level (use for debugging)

    Pull a signal to the top level (use for debugging)

    Definition Classes
    Data
  149. def purify(): MemBus.this.type
    Definition Classes
    Data
  150. def randBoot(u: Unit): MemBus.this.type

    Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)

    Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)

    Definition Classes
    Data
  151. val rdat: Bits
  152. val refOwner: RefOwnerType
    Definition Classes
    OwnableRef
    Annotations
    @DontName()
  153. def reflectNames(): Unit
    Definition Classes
    Nameable
  154. def removeAssignments(data: Boolean = true, init: Boolean = true, initial: Boolean = true): MemBus.this.type
    Definition Classes
    Data
  155. def removeDataAssignments(): MemBus.this.type
    Definition Classes
    Data
  156. def removeInitAssignments(): MemBus.this.type
    Definition Classes
    Data
  157. def removeTag(spinalTag: SpinalTag): MemBus.this.type
    Definition Classes
    SpinalTagReady
  158. def removeTags(tags: Iterable[SpinalTag]): MemBus.this.type
    Definition Classes
    SpinalTagReady
  159. def resized: MemBus.this.type

    Return a version of the signal which is allowed to be automatically resized where needed.

    Return a version of the signal which is allowed to be automatically resized where needed.

    The resize operation is deferred until the point of assignment later. The resize may widen or truncate, retaining the LSB.

    Definition Classes
    Data
    See also

    Width checking Documentation

  160. def rootIF(): Interface

    root interface

    root interface

    Definition Classes
    Data
  161. def rootIFList(): List[Interface]
    Definition Classes
    Data
  162. def rootIFrec(now: Data, lastRoot: List[Interface]): List[Interface]
    Definition Classes
    Data
  163. val scalaTrace: Throwable
    Definition Classes
    ScalaLocated
  164. def setAll(): MemBus.this.type

    Set all bits to True and return itself

    Set all bits to True and return itself

    Definition Classes
    Data
  165. def setAsAnalog(): MemBus.this.type
    Definition Classes
    Data
  166. def setAsComb(): MemBus.this.type

    Set baseType to Combinatorial

    Set baseType to Combinatorial

    Definition Classes
    MultiData → Data
  167. def setAsDirectionLess(): MemBus.this.type

    Remove the direction (in, out, inout) to a signal

    Remove the direction (in, out, inout) to a signal

    Definition Classes
    MultiData → Data
  168. final def setAsMaster(): Unit

    Set as master interface

    Set as master interface

    Definition Classes
    IMasterSlave
  169. def setAsReg(): MemBus.this.type

    Set baseType to reg

    Set baseType to reg

    Definition Classes
    MultiData → Data
  170. final def setAsSlave(): Unit

    Set a slave interface

    Set a slave interface

    Definition Classes
    IMasterSlave
  171. def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): MemBus.this.type
    Definition Classes
    Nameable
  172. def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): MemBus.this.type
    Definition Classes
    Nameable
  173. def setCompositeName(nameable: Nameable, postfix: String): MemBus.this.type
    Definition Classes
    Nameable
  174. def setCompositeName(nameable: Nameable, namePriority: Byte): MemBus.this.type
    Definition Classes
    Nameable
  175. def setCompositeName(nameable: Nameable, weak: Boolean): MemBus.this.type
    Definition Classes
    Nameable
  176. def setCompositeName(nameable: Nameable): MemBus.this.type
    Definition Classes
    Nameable
  177. def setDefinitionName(name: String): MemBus.this.type

    Set the definition name of the component

    Set the definition name of the component

    Definition Classes
    Interface
  178. def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): MemBus.this.type
    Definition Classes
    Nameable
  179. def setName(name: String, namePriority: Byte): MemBus.this.type
    Definition Classes
    Nameable
  180. def setName(name: String, weak: Boolean): MemBus.this.type
    Definition Classes
    Nameable
  181. def setName(name: String): MemBus.this.type
    Definition Classes
    Nameable
  182. def setNameAsWeak(): MemBus.this.type
    Definition Classes
    Nameable
  183. def setOutputAsReg(): MemBus.this.type

    Recursively set baseType to reg only for output

    Recursively set baseType to reg only for output

    Definition Classes
    Data
  184. def setPartialName(name: String, namePriority: Byte, owner: Any): MemBus.this.type
    Definition Classes
    Nameable
  185. def setPartialName(name: String, namePriority: Byte): MemBus.this.type
    Definition Classes
    Nameable
  186. def setPartialName(name: String, weak: Boolean): MemBus.this.type
    Definition Classes
    Nameable
  187. def setPartialName(owner: Nameable, name: String, namePriority: Byte): MemBus.this.type
    Definition Classes
    Nameable
  188. def setPartialName(owner: Nameable, name: String, weak: Boolean): MemBus.this.type
    Definition Classes
    Nameable
  189. def setPartialName(name: String): MemBus.this.type
    Definition Classes
    Nameable
  190. def setPartialName(owner: Nameable, name: String): MemBus.this.type
    Definition Classes
    Nameable
  191. def setPartialName(owner: Nameable): MemBus.this.type
    Definition Classes
    Nameable
  192. def setRefOwner(that: Any): Unit
    Definition Classes
    OwnableRef
  193. def setScalaLocated(source: ScalaLocated): MemBus.this.type
    Definition Classes
    ScalaLocated
  194. def setWeakName(name: String): MemBus.this.type
    Definition Classes
    Nameable
  195. def slv: Unit
    Annotations
    @modport()
  196. def spinalTags: LinkedHashSet[SpinalTag]
    Definition Classes
    SpinalTagReady
  197. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  198. var thisIsNotSVIF: Boolean
    Definition Classes
    Interface
  199. def tieGeneric[T <: BitVector](signal: T, generic: String): LinkedHashMap[BitVector, String]
    Definition Classes
    Interface
  200. def tieIFParameter[T <: Interface](signal: T, signalParam: String, inputParam: String): LinkedHashMap[(Data, String), String]
    Definition Classes
    Interface
  201. def tieParameter[T <: BitVector](signal: T, parameter: String): LinkedHashMap[BitVector, String]
    Definition Classes
    Interface
  202. def toIo(): MemBus.this.type
    Definition Classes
    Data
  203. def toMuxInput[T <: Data](muxOutput: T): T
    Definition Classes
    Data
  204. def toString(): String
    Definition Classes
    Bundle → Nameable → AnyRef → Any
  205. def unfreeze(): MemBus.this.type
    Definition Classes
    MultiData → Data
  206. def unsetName(): MemBus.this.type
    Definition Classes
    Nameable
  207. def valCallback[T](ref: T, name: String): T
    Definition Classes
    ValCallbackRec → ValCallback
  208. def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit
    Definition Classes
    ValCallbackRec
  209. def valCallbackRec(ref: Any, name: String): Unit
    Definition Classes
    Interface → Bundle → ValCallbackRec
  210. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  211. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  212. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  213. val wdat: Bits
  214. val widthGeneric: LinkedHashMap[BitVector, String]
    Definition Classes
    Interface
  215. val wr: Bool
  216. def wrapNext(): MemBus.this.type
    Definition Classes
    Data
  217. def zipByName(that: MultiData, rec: ArrayBuffer[(BaseType, BaseType)] = ArrayBuffer()): ArrayBuffer[(BaseType, BaseType)]
    Definition Classes
    MultiData

Deprecated Value Members

  1. def asDirectionLess(): MemBus.this.type
    Definition Classes
    Data
    Annotations
    @deprecated
    Deprecated

    (Since version ???) use setAsDirectionLess instead

  2. def asMaster(): Unit

    Override it to define port directions for a master interface.

    Override it to define port directions for a master interface.

    Definition Classes
    MemBus → IMasterSlave
    Deprecated

    This method must be overriden but not called. Calling this method is not correct. Call setAsMaster() or intoMaster() instead. This method is named asXxx but it does not return Xxx. This method does not update isMasterInterface and isSlaveInterface.

  3. def asSlave(): Unit

    Override it to define port directions for a master interface.

    Override it to define port directions for a master interface.

    If not overriden, defaults to the opposite port directions of asMaster().

    Definition Classes
    IMasterSlave
    Deprecated

    This method can be overriden but not called. Calling this method is not correct. Call setAsSlave() or intoSlave() instead. This method is named asXxx but it does not return Xxx. This method does not update isMasterInterface and isSlaveInterface.

  4. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated
  5. def genIf(cond: Boolean): MemBus.this.type

    Generate this if condition is true

    Generate this if condition is true

    Definition Classes
    Data
    Annotations
    @deprecated
    Deprecated

    does not work with <>, use 'someBool generate Type()' or 'if(condition) Type() else null' instead

Inherited from Serializable

Inherited from Serializable

Inherited from Product

Inherited from Equals

Inherited from IMasterSlave

Inherited from Interface

Inherited from Bundle

Inherited from ValCallbackRec

Inherited from ValCallback

Inherited from MultiData

Inherited from Data

Inherited from InComponent

Inherited from OverridedEqualsHashCode

Inherited from SpinalTagReady

Inherited from Assignable

Inherited from NameableByComponent

Inherited from Nameable

Inherited from OwnableRef

Inherited from ContextUser

Inherited from ScalaLocated

Inherited from GlobalDataUser

Inherited from AnyRef

Inherited from Any

Ungrouped