case class ClockDomainConfig(clockEdge: EdgeKind = RISING, resetKind: ResetKind = ASYNC, resetActiveLevel: Polarity = HIGH, softResetActiveLevel: Polarity = HIGH, clockEnableActiveLevel: Polarity = HIGH) extends Product with Serializable
The caracteristic (rising, async, high, e.g.) of the control signals of a ClockDomain
- clockEdge
- resetKind
can be ASYNC (default), SYNC or BOOT which is supported by some FPGAs (where FF values are loaded by the bitstream)
- resetActiveLevel
- softResetActiveLevel
- clockEnableActiveLevel
- See also
Linear Supertypes
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- val resetActiveLevel: Polarity
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