case class WishboneBusInterface(bus: Wishbone, sizeMap: SizeMapping, readSync: Boolean = true, regPre: String = "", withSecFireWall: Boolean = false)(implicit moduleName: ClassName) extends BusIf with Product with Serializable
Linear Supertypes
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Inherited
- WishboneBusInterface
- Serializable
- Serializable
- Product
- Equals
- BusIf
- BusIfBase
- Area
- OverridedEqualsHashCode
- ValCallbackRec
- ValCallback
- NameableByComponent
- Nameable
- ContextUser
- ScalaLocated
- GlobalDataUser
- OwnableRef
- AnyRef
- Any
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Visibility
- Public
- All
Instance Constructors
- new WishboneBusInterface(bus: Wishbone, sizeMap: SizeMapping, readSync: Boolean = true, regPre: String = "", withSecFireWall: Boolean = false)(implicit moduleName: ClassName)
Type Members
-
abstract
type
B <: WishboneBusInterface.this.type
- Definition Classes
- BusIf
-
abstract
type
RefOwnerType
- Definition Classes
- OwnableRef
Value Members
-
final
def
!=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
final
def
##(): Int
- Definition Classes
- AnyRef → Any
-
final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
def
FifoInsts: ListBuffer[FifoInst]
- Definition Classes
- BusIf
-
def
RamInsts: ListBuffer[RamInst]
- Definition Classes
- BusIf
-
def
RegAndFifos: List[RegSlice]
- Definition Classes
- BusIf
-
def
RegInsts: ListBuffer[RegInst]
- Definition Classes
- BusIf
-
val
_addrAlignCheck: Boolean
- Attributes
- protected
- Definition Classes
- BusIfBase
-
val
_context: Capture
- Definition Classes
- Area
-
def
accept(doc: BusIfDoc): Unit
- Definition Classes
- BusIf
- val ack: Bool
-
def
addrAlignCheck(address: BigInt): Unit
- Definition Classes
- BusIf
-
def
addressUsed(addr: BigInt): Boolean
- Definition Classes
- BusIf
-
final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
-
val
askRead: Bool
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
askWrite: Bool
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
blockId: Int
- Attributes
- protected
- Definition Classes
- BusIf
-
def
blockIdInc(): Unit
- Attributes
- protected
- Definition Classes
- BusIf
-
val
bus: Wishbone
- Definition Classes
- WishboneBusInterface → BusIf
-
val
busAddrWidth: Int
- Definition Classes
- WishboneBusInterface → BusIfBase
-
def
busByteWidth: Int
- Definition Classes
- BusIfBase
-
val
busDataWidth: Int
- Definition Classes
- WishboneBusInterface → BusIfBase
-
def
busName: String
- Definition Classes
- BusIf
-
lazy val
bus_nsbit: Bool
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
bus_rdata: Bits
- Definition Classes
- WishboneBusInterface → BusIfBase
-
def
bus_slverr: Bool
- Definition Classes
- BusIfBase
-
def
bw: Int
- Definition Classes
- BusIfBase
- val byteAddress: UInt
-
lazy val
cg_en: Bool
- Definition Classes
- BusIfBase
-
def
childNamePriority: Byte
- Definition Classes
- Area
-
def
clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native() @IntrinsicCandidate()
-
def
component: Component
- Definition Classes
- ContextUser
-
def
createGrp(name: String, addr: BigInt, maxSize: BigInt, doc: String, sec: Secure = null): RegSliceGrp
- Definition Classes
- BusIf
-
def
createRAM(name: String, addr: BigInt, size: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null): RamInst
- Definition Classes
- BusIf
-
def
createRdFifo(name: String, addr: BigInt, Doc: String, sec: Secure = null, grp: GrpTag = null): RdFifoInst
- Definition Classes
- BusIf
-
def
createReg(name: String, addr: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null): RegInst
- Definition Classes
- BusIf
-
def
createWrFifo(name: String, addr: BigInt, Doc: String, sec: Secure = null, grp: GrpTag = null): WrFifoInst
- Definition Classes
- BusIf
-
def
defaultReadBits: Bits
- Definition Classes
- BusIf
-
val
doRead: Bool
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
doWrite: Bool
- Definition Classes
- WishboneBusInterface → BusIfBase
-
def
docPath: String
- Definition Classes
- BusIf
-
final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
def
equals(obj: Any): Boolean
- Definition Classes
- OverridedEqualsHashCode → AnyRef → Any
-
def
foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit
- Definition Classes
- Nameable
-
def
gen(doc: BusIfDoc): Unit
- Definition Classes
- BusIf
-
def
genBaseDocs(docname: String, prefix: String = ""): Unit
- Definition Classes
- BusIf
-
def
getAddrMap: List[String]
- Definition Classes
- BusIf
-
final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
-
def
getCurrentBlockTag: ReuseTag
- Definition Classes
- BusIf
-
def
getDisplayName(): String
- Definition Classes
- Nameable
-
def
getInstanceCounter: Int
- Definition Classes
- ContextUser
-
def
getMode: Byte
- Attributes
- protected
- Definition Classes
- Nameable
-
def
getModuleName: String
- Definition Classes
- WishboneBusInterface → BusIf
-
def
getName(default: String): String
- Definition Classes
- NameableByComponent → Nameable
-
def
getName(): String
- Definition Classes
- NameableByComponent → Nameable
-
def
getOrCreateSecLogic(key: Bool, logic: Bool): Bool
- Definition Classes
- BusIf
-
def
getPartialName(): String
- Definition Classes
- Nameable
-
def
getPath(from: Component, to: Component): Seq[Component]
- Definition Classes
- NameableByComponent
-
def
getRefOwnersChain(): List[Any]
- Definition Classes
- OwnableRef
-
def
getRegPtr(): BigInt
- Definition Classes
- BusIf
-
def
getReservedAddressReadValue: BigInt
- Definition Classes
- BusIf
-
def
getScalaLocationLong: String
- Definition Classes
- ScalaLocated
-
def
getScalaLocationShort: String
- Definition Classes
- ScalaLocated
-
def
getScalaTrace(): Throwable
- Definition Classes
- ScalaLocated
-
def
getSecFailReadValue: BigInt
- Definition Classes
- BusIf
-
def
getVersion: String
- Definition Classes
- BusIfBase
-
val
globalData: GlobalData
- Definition Classes
- GlobalDataUser
-
val
grpId: Int
- Attributes
- protected
- Definition Classes
- BusIf
-
def
grpIdInc(): Unit
- Attributes
- protected
- Definition Classes
- BusIf
- val halted: Bool
-
def
hasBlock: Boolean
- Definition Classes
- BusIf
-
def
hashCode(): Int
- Definition Classes
- OverridedEqualsHashCode → AnyRef → Any
-
def
initStrbMasks(): Unit
- Definition Classes
- BusIfBase
-
def
isCompletelyUnnamed: Boolean
- Definition Classes
- Nameable
-
final
def
isInstanceOf[T0]: Boolean
- Definition Classes
- Any
-
final
def
isNamed: Boolean
- Definition Classes
- Nameable
-
def
isPriorityApplicable(namePriority: Byte): Boolean
- Definition Classes
- Nameable
-
def
isUnnamed: Boolean
- Definition Classes
- NameableByComponent → Nameable
-
def
mwdata(pos: Int): Bool
- Definition Classes
- BusIfBase
-
def
mwdata(sec: Range): Bits
- Definition Classes
- BusIfBase
-
val
name: String
- Definition Classes
- Nameable
- val nameableRef: Nameable
-
final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
def
newBlockTag(instName: String)(partName: String): ReuseTag
- Definition Classes
- BusIf
-
def
newBlockTagAt(addr: BigInt, instName: String)(partName: String): ReuseTag
- Definition Classes
- BusIf
-
def
newGrp(maxSize: BigInt, doc: String, sec: Secure = null)(implicit symbol: SymbolName): RegSliceGrp
- Definition Classes
- BusIf
-
def
newGrpAt(address: BigInt, maxSize: BigInt, doc: String, sec: Secure = null)(implicit symbol: SymbolName): RegSliceGrp
- Definition Classes
- BusIf
-
def
newGrpTag(name: String): GrpTag
- Definition Classes
- BusIf
-
def
newRAM(size: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RamInst
- Definition Classes
- BusIf
-
def
newRAMAt(address: BigInt, size: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RamInst
- Definition Classes
- BusIf
-
def
newRdFifo(doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RdFifoInst
- Definition Classes
- BusIf
-
def
newRdFifoAt(address: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RdFifoInst
- Definition Classes
- BusIf
-
def
newReg(doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RegInst
- Definition Classes
- BusIf
-
def
newRegAt(address: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RegInst
- Definition Classes
- BusIf
-
def
newWrFifo(doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): WrFifoInst
- Definition Classes
- BusIf
-
def
newWrFifoAt(address: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): WrFifoInst
- Definition Classes
- BusIf
-
final
def
notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
-
final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
-
def
orderdRegInsts: ListBuffer[RegSlice]
- Definition Classes
- BusIf
-
def
overrideLocalName(name: String): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
val
parentScope: ScopeStatement
- Definition Classes
- ContextUser
-
def
preCheck(): Unit
- Definition Classes
- BusIf
-
def
readAddress(): UInt
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
readDefaultValue: BigInt
- Attributes
- protected
- Definition Classes
- BusIf
-
def
readHalt(): Unit
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
readSync: Boolean
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
refOwner: RefOwnerType
- Definition Classes
- OwnableRef
- Annotations
- @DontName()
-
def
reflectNames(): Unit
- Definition Classes
- Nameable
-
def
regPart(name: String)(block: ⇒ Unit): Unit
- Definition Classes
- BusIf
-
val
regPre: String
- Definition Classes
- WishboneBusInterface → BusIf
-
def
regPtrReAnchorAt(pos: BigInt): Unit
- Definition Classes
- BusIf
-
def
regSlicesNotReuse: List[RegSlice]
- Definition Classes
- BusIf
-
val
reg_rdata: Bits
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
reg_rderr: Bool
- Definition Classes
- WishboneBusInterface → BusIfBase
-
lazy val
reg_wrerr: Bool
- Definition Classes
- WishboneBusInterface → BusIfBase
-
def
repeatGroupsBase: Map[String, List[RegSlice]]
- Definition Classes
- BusIf
-
def
repeatGroupsHead: Map[String, List[RegSlice]]
- Definition Classes
- BusIf
-
def
resetBlockTag(): Unit
- Definition Classes
- BusIf
-
def
reuseGroups: Map[String, List[RegSlice]]
- Definition Classes
- BusIf
-
def
reuseGroupsById: Map[String, Map[Int, List[RegSlice]]]
- Definition Classes
- BusIf
-
def
rework[T](body: ⇒ T): T
- Definition Classes
- Area
-
val
scalaTrace: Throwable
- Definition Classes
- ScalaLocated
-
def
secFailDefaultBits: Bits
- Definition Classes
- BusIf
-
val
secFailReadValue: BigInt
- Attributes
- protected
- Definition Classes
- BusIf
-
def
setAlignCheck(value: Boolean = false): Unit
- Definition Classes
- BusIfBase
-
def
setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, postfix: String): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, namePriority: Byte): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, weak: Boolean): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setName(name: String, namePriority: Byte): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setName(name: String, weak: Boolean): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setName(name: String): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setNameAsWeak(): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String, namePriority: Byte, owner: Any): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String, namePriority: Byte): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String, weak: Boolean): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String, namePriority: Byte): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String, weak: Boolean): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
setRefOwner(that: Any): Unit
- Definition Classes
- OwnableRef
-
def
setReservedAddressReadValue(value: BigInt): Unit
- Definition Classes
- BusIf
-
def
setScalaLocated(source: ScalaLocated): WishboneBusInterface.this.type
- Definition Classes
- ScalaLocated
-
def
setSecFailReadValue(value: BigInt): Unit
- Definition Classes
- BusIf
-
def
setVersion(ver: String): Unit
- Definition Classes
- BusIfBase
-
def
setWeakName(name: String): WishboneBusInterface.this.type
- Definition Classes
- Nameable
- val sizeMap: SizeMapping
-
def
slices: List[RegSlice]
- Definition Classes
- BusIf
-
def
strbWidth: Int
- Definition Classes
- BusIfBase
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
- def toString(): String
-
def
underbitWidth: Int
- Definition Classes
- BusIfBase
-
def
unsetName(): WishboneBusInterface.this.type
- Definition Classes
- Nameable
-
def
valCallback[T](ref: T, name: String): T
- Definition Classes
- ValCallbackRec → ValCallback
-
def
valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit
- Definition Classes
- ValCallbackRec
-
def
valCallbackRec(obj: Any, name: String): Unit
- Definition Classes
- Area → ValCallbackRec
-
final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
final
def
wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native()
-
final
def
wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
def
wdata(reg: Bool, pos: Int, oper: String): Bool
- Definition Classes
- BusIfBase
-
def
wdata(reg: Bool, pos: Int): Bool
- Definition Classes
- BusIfBase
-
def
wdata(reg: BaseType, sec: Range, oper: String): Bits
- Definition Classes
- BusIfBase
-
def
wdata(reg: BaseType, sec: Range): Bits
- Definition Classes
- BusIfBase
-
val
withSecFireWall: Boolean
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
withStrb: Boolean
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
wmask: Bits
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
wmaskn: Bits
- Definition Classes
- WishboneBusInterface → BusIfBase
-
def
wordAddressInc: Int
- Definition Classes
- BusIfBase
-
def
writeAddress(): UInt
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
writeData: Bits
- Definition Classes
- WishboneBusInterface → BusIfBase
-
def
writeHalt(): Unit
- Definition Classes
- WishboneBusInterface → BusIfBase
-
val
wstrb: Bits
- Definition Classes
- WishboneBusInterface → BusIfBase
Deprecated Value Members
-
def
creatReg(name: String, addr: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null): RegInst
- Definition Classes
- BusIf
- Annotations
- @deprecated
- Deprecated
(Since version 2024.06.03) type error fix
-
def
finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( classOf[java.lang.Throwable] ) @Deprecated
- Deprecated
-
lazy val
readData: Bits
- Definition Classes
- BusIfBase
- Annotations
- @deprecated
- Deprecated
(Since version 2024.12.30) readData rename to bus_rdata
-
lazy val
readError: Bool
- Definition Classes
- BusIfBase
- Annotations
- @deprecated
- Deprecated
(Since version 2024.12.30) readError rename to bus_rderr