c

spinal.lib.bus.regif

AxiLite4BusInterface

case class AxiLite4BusInterface(bus: AxiLite4, sizeMap: SizeMapping, regPre: String = "", withSecFireWall: Boolean = false)(implicit moduleName: ClassName) extends BusIf with Product with Serializable

Linear Supertypes
Serializable, Serializable, Product, Equals, BusIf, BusIfBase, Area, OverridedEqualsHashCode, ValCallbackRec, ValCallback, NameableByComponent, Nameable, ContextUser, ScalaLocated, GlobalDataUser, OwnableRef, AnyRef, Any
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  2. By Inheritance
Inherited
  1. AxiLite4BusInterface
  2. Serializable
  3. Serializable
  4. Product
  5. Equals
  6. BusIf
  7. BusIfBase
  8. Area
  9. OverridedEqualsHashCode
  10. ValCallbackRec
  11. ValCallback
  12. NameableByComponent
  13. Nameable
  14. ContextUser
  15. ScalaLocated
  16. GlobalDataUser
  17. OwnableRef
  18. AnyRef
  19. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new AxiLite4BusInterface(bus: AxiLite4, sizeMap: SizeMapping, regPre: String = "", withSecFireWall: Boolean = false)(implicit moduleName: ClassName)

Type Members

  1. abstract type B <: AxiLite4BusInterface.this.type
    Definition Classes
    BusIf
  2. abstract type RefOwnerType
    Definition Classes
    OwnableRef

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def FifoInsts: ListBuffer[FifoInst]
    Definition Classes
    BusIf
  5. def RamInsts: ListBuffer[RamInst]
    Definition Classes
    BusIf
  6. def RegAndFifos: List[RegSlice]
    Definition Classes
    BusIf
  7. def RegInsts: ListBuffer[RegInst]
    Definition Classes
    BusIf
  8. val _addrAlignCheck: Boolean
    Attributes
    protected
    Definition Classes
    BusIfBase
  9. val _context: Capture
    Definition Classes
    Area
  10. def accept(doc: BusIfDoc): Unit
    Definition Classes
    BusIf
  11. val accessDefaultError: Boolean
    Attributes
    protected
    Definition Classes
    BusIf
  12. def addrAlignCheck(address: BigInt): Unit
    Definition Classes
    BusIf
  13. def addressUsed(addr: BigInt): Boolean
    Definition Classes
    BusIf
  14. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  15. val askRead: Bool
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  16. val askWrite: Bool
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  17. val axiAr: Stream[AxiLite4Ax]
  18. val axiAw: Stream[AxiLite4Ax]
  19. val axiB: Stream[AxiLite4B]
  20. val axiBValid: Bool
  21. val axiR: Stream[AxiLite4R]
  22. val axiRValid: Bool
  23. val axiW: Stream[AxiLite4W]
  24. val blockId: Int
    Attributes
    protected
    Definition Classes
    BusIf
  25. def blockIdInc(): Unit
    Attributes
    protected
    Definition Classes
    BusIf
  26. val bus: AxiLite4
    Definition Classes
    AxiLite4BusInterface → BusIf
  27. val busAddrWidth: Int
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  28. def busByteWidth: Int
    Definition Classes
    BusIfBase
  29. val busDataWidth: Int
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  30. def busName: String
    Definition Classes
    BusIf
  31. val bus_err: Bool
  32. lazy val bus_nsbit: Bool
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  33. val bus_rdata: Bits
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  34. def bus_slverr: Bool
    Definition Classes
    BusIfBase
  35. def bw: Int
    Definition Classes
    BusIfBase
  36. lazy val cg_en: Bool
    Definition Classes
    BusIfBase
  37. def childNamePriority: Byte
    Definition Classes
    Area
  38. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @IntrinsicCandidate()
  39. def component: Component
    Definition Classes
    ContextUser
  40. def createGrp(name: String, addr: BigInt, maxSize: BigInt, doc: String, sec: Secure = null): RegSliceGrp
    Definition Classes
    BusIf
  41. def createRAM(name: String, addr: BigInt, size: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null): RamInst
    Definition Classes
    BusIf
  42. def createRdFifo(name: String, addr: BigInt, Doc: String, sec: Secure = null, grp: GrpTag = null): RdFifoInst
    Definition Classes
    BusIf
  43. def createReg(name: String, addr: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null): RegInst
    Definition Classes
    BusIf
  44. def createWrFifo(name: String, addr: BigInt, Doc: String, sec: Secure = null, grp: GrpTag = null): WrFifoInst
    Definition Classes
    BusIf
  45. def defaultReadBits: Bits
    Definition Classes
    BusIf
  46. val doRead: Bool
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  47. val doWrite: Bool
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  48. def docPath: String
    Definition Classes
    BusIf
  49. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  50. def equals(obj: Any): Boolean
    Definition Classes
    OverridedEqualsHashCode → AnyRef → Any
  51. def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit
    Definition Classes
    Nameable
  52. def gen(doc: BusIfDoc): Unit
    Definition Classes
    BusIf
  53. def genBaseDocs(docname: String, prefix: String = ""): Unit
    Definition Classes
    BusIf
  54. def getAddrMap: List[String]
    Definition Classes
    BusIf
  55. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  56. def getCurrentBlockTag: ReuseTag
    Definition Classes
    BusIf
  57. def getDisplayName(): String
    Definition Classes
    Nameable
  58. def getInstanceCounter: Int
    Definition Classes
    ContextUser
  59. def getMode: Byte
    Attributes
    protected
    Definition Classes
    Nameable
  60. def getModuleName: String
    Definition Classes
    AxiLite4BusInterface → BusIf
  61. def getName(default: String): String
    Definition Classes
    NameableByComponent → Nameable
  62. def getName(): String
    Definition Classes
    NameableByComponent → Nameable
  63. def getOrCreateSecLogic(key: Bool, logic: Bool): Bool
    Definition Classes
    BusIf
  64. def getPartialName(): String
    Definition Classes
    Nameable
  65. def getPath(from: Component, to: Component): Seq[Component]
    Definition Classes
    NameableByComponent
  66. def getRefOwnersChain(): List[Any]
    Definition Classes
    OwnableRef
  67. def getRegPtr(): BigInt
    Definition Classes
    BusIf
  68. def getReservedAddressErrorState: Boolean
    Definition Classes
    BusIf
  69. def getReservedAddressReadValue: BigInt
    Definition Classes
    BusIf
  70. def getScalaLocationLong: String
    Definition Classes
    ScalaLocated
  71. def getScalaLocationShort: String
    Definition Classes
    ScalaLocated
  72. def getScalaTrace(): Throwable
    Definition Classes
    ScalaLocated
  73. def getSecFailReadValue: BigInt
    Definition Classes
    BusIf
  74. def getVersion: String
    Definition Classes
    BusIfBase
  75. val globalData: GlobalData
    Definition Classes
    GlobalDataUser
  76. def groupConsecutiveBlocks(blocks: List[List[RegSlice]]): List[(List[RegSlice], Int, Int)]

    Gap-aware run-length encoding algorithm (Enhanced: Added block size consistency check)

    Gap-aware run-length encoding algorithm (Enhanced: Added block size consistency check)

    blocks

    Input list of blocks, each block is a consecutive list of Reg

    returns

    List of triples (first block, consecutive block count, interval)

    Definition Classes
    BusIfBase
  77. val grpId: Int
    Attributes
    protected
    Definition Classes
    BusIf
  78. def grpIdInc(): Unit
    Attributes
    protected
    Definition Classes
    BusIf
  79. def grupConsecutiveBlocks(blocks: List[List[RegSlice]], tolerance: Int): List[(List[RegSlice], Int, Int)]
    Definition Classes
    BusIfBase
  80. def hasBlock: Boolean
    Definition Classes
    BusIf
  81. def hashCode(): Int
    Definition Classes
    OverridedEqualsHashCode → AnyRef → Any
  82. def initStrbMasks(): Unit
    Definition Classes
    BusIfBase
  83. def isCompletelyUnnamed: Boolean
    Definition Classes
    Nameable
  84. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  85. final def isNamed: Boolean
    Definition Classes
    Nameable
  86. def isPriorityApplicable(namePriority: Byte): Boolean
    Definition Classes
    Nameable
  87. def isUnnamed: Boolean
    Definition Classes
    NameableByComponent → Nameable
  88. def mwdata(pos: Int): Bool
    Definition Classes
    BusIfBase
  89. def mwdata(sec: Range): Bits
    Definition Classes
    BusIfBase
  90. val name: String
    Definition Classes
    Nameable
  91. val nameableRef: Nameable
    Attributes
    protected
    Definition Classes
    Nameable
    Annotations
    @DontName()
  92. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  93. def newBlockTag(instName: String)(partName: String): ReuseTag
    Definition Classes
    BusIf
  94. def newBlockTagAt(addr: BigInt, instName: String)(partName: String): ReuseTag
    Definition Classes
    BusIf
  95. def newGrp(maxSize: BigInt, doc: String, sec: Secure = null)(implicit symbol: SymbolName): RegSliceGrp
    Definition Classes
    BusIf
  96. def newGrpAt(address: BigInt, maxSize: BigInt, doc: String, sec: Secure = null)(implicit symbol: SymbolName): RegSliceGrp
    Definition Classes
    BusIf
  97. def newGrpTag(name: String): GrpTag
    Definition Classes
    BusIf
  98. def newRAM(size: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RamInst
    Definition Classes
    BusIf
  99. def newRAMAt(address: BigInt, size: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RamInst
    Definition Classes
    BusIf
  100. def newRdFifo(doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RdFifoInst
    Definition Classes
    BusIf
  101. def newRdFifoAt(address: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RdFifoInst
    Definition Classes
    BusIf
  102. def newReg(doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RegInst
    Definition Classes
    BusIf
  103. def newRegAt(address: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): RegInst
    Definition Classes
    BusIf
  104. def newWrFifo(doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): WrFifoInst
    Definition Classes
    BusIf
  105. def newWrFifoAt(address: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null)(implicit symbol: SymbolName): WrFifoInst
    Definition Classes
    BusIf
  106. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  107. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  108. def orderdRegInsts: ListBuffer[RegSlice]
    Definition Classes
    BusIf
  109. def overrideLocalName(name: String): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  110. val parentScope: ScopeStatement
    Definition Classes
    ContextUser
  111. def preCheck(): Unit
    Definition Classes
    BusIf
  112. def readAddress(): UInt
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  113. val readDefaultValue: BigInt
    Attributes
    protected
    Definition Classes
    BusIf
  114. def readHalt(): Unit
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  115. val readSync: Boolean
    Definition Classes
    BusIfBase
  116. val refOwner: RefOwnerType
    Definition Classes
    OwnableRef
    Annotations
    @DontName()
  117. def reflectNames(): Unit
    Definition Classes
    Nameable
  118. def regPart(name: String)(block: ⇒ Unit): Unit
    Definition Classes
    BusIf
  119. val regPre: String
    Definition Classes
    AxiLite4BusInterface → BusIf
  120. def regPtrReAnchorAt(pos: BigInt): Unit
    Definition Classes
    BusIf
  121. def regSlicesNotReuse: List[RegSlice]
    Definition Classes
    BusIf
  122. val reg_rdata: Bits
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  123. val reg_rderr: Bool
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  124. lazy val reg_wrerr: Bool
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  125. def repeatGroupsBase: Map[String, List[RegSlice]]
    Definition Classes
    BusIf
  126. def repeatGroupsHead: Map[String, List[RegSlice]]
    Definition Classes
    BusIf
  127. def resetBlockTag(): Unit
    Definition Classes
    BusIf
  128. def reuseGroups: Map[String, List[RegSlice]]
    Definition Classes
    BusIf
  129. def reuseGroupsById: Map[String, Map[Int, List[RegSlice]]]
    Definition Classes
    BusIf
  130. def rework[T](body: ⇒ T): T
    Definition Classes
    Area
  131. val scalaTrace: Throwable
    Definition Classes
    ScalaLocated
  132. def secFailDefaultBits: Bits
    Definition Classes
    BusIf
  133. val secFailReadValue: BigInt
    Attributes
    protected
    Definition Classes
    BusIf
  134. def setAlignCheck(value: Boolean = false): Unit
    Definition Classes
    BusIfBase
  135. def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  136. def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  137. def setCompositeName(nameable: Nameable, postfix: String): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  138. def setCompositeName(nameable: Nameable, namePriority: Byte): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  139. def setCompositeName(nameable: Nameable, weak: Boolean): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  140. def setCompositeName(nameable: Nameable): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  141. def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  142. def setName(name: String, namePriority: Byte): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  143. def setName(name: String, weak: Boolean): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  144. def setName(name: String): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  145. def setNameAsWeak(): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  146. def setPartialName(name: String, namePriority: Byte, owner: Any): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  147. def setPartialName(name: String, namePriority: Byte): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  148. def setPartialName(name: String, weak: Boolean): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  149. def setPartialName(owner: Nameable, name: String, namePriority: Byte): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  150. def setPartialName(owner: Nameable, name: String, weak: Boolean): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  151. def setPartialName(name: String): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  152. def setPartialName(owner: Nameable, name: String): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  153. def setPartialName(owner: Nameable): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  154. def setRefOwner(that: Any): Unit
    Definition Classes
    OwnableRef
  155. def setReservedAddressErrorState(state: Boolean): Unit
    Definition Classes
    BusIf
  156. def setReservedAddressReadValue(value: BigInt): Unit
    Definition Classes
    BusIf
  157. def setScalaLocated(source: ScalaLocated): AxiLite4BusInterface.this.type
    Definition Classes
    ScalaLocated
  158. def setSecFailReadValue(value: BigInt): Unit
    Definition Classes
    BusIf
  159. def setVersion(ver: String): Unit
    Definition Classes
    BusIfBase
  160. def setWeakName(name: String): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  161. val sizeMap: SizeMapping
  162. def slices: List[RegSlice]
    Definition Classes
    BusIf
  163. def strbWidth: Int
    Definition Classes
    BusIfBase
  164. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  165. def toString(): String
    Definition Classes
    Area → Nameable → AnyRef → Any
  166. def underbitWidth: Int
    Definition Classes
    BusIfBase
  167. def unsetName(): AxiLite4BusInterface.this.type
    Definition Classes
    Nameable
  168. def valCallback[T](ref: T, name: String): T
    Definition Classes
    ValCallbackRec → ValCallback
  169. def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit
    Definition Classes
    ValCallbackRec
  170. def valCallbackRec(obj: Any, name: String): Unit
    Definition Classes
    Area → ValCallbackRec
  171. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  172. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  173. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  174. def wdata(reg: Bool, pos: Int, oper: String): Bool
    Definition Classes
    BusIfBase
  175. def wdata(reg: Bool, pos: Int): Bool
    Definition Classes
    BusIfBase
  176. def wdata(reg: BaseType, sec: Range, oper: String): Bits
    Definition Classes
    BusIfBase
  177. def wdata(reg: BaseType, sec: Range): Bits
    Definition Classes
    BusIfBase
  178. val withSecFireWall: Boolean
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  179. val withStrb: Boolean
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  180. val wmask: Bits
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  181. val wmaskn: Bits
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  182. def wordAddressInc: Int
    Definition Classes
    BusIfBase
  183. def writeAddress(): UInt
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  184. val writeData: Bits
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  185. def writeHalt(): Unit
    Definition Classes
    AxiLite4BusInterface → BusIfBase
  186. val wstrb: Bits
    Definition Classes
    AxiLite4BusInterface → BusIfBase

Deprecated Value Members

  1. def creatReg(name: String, addr: BigInt, doc: String, sec: Secure = null, grp: GrpTag = null): RegInst
    Definition Classes
    BusIf
    Annotations
    @deprecated
    Deprecated

    (Since version 2024.06.03) type error fix

  2. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated
  3. lazy val readData: Bits
    Definition Classes
    BusIfBase
    Annotations
    @deprecated
    Deprecated

    (Since version 2024.12.30) readData rename to bus_rdata

  4. lazy val readError: Bool
    Definition Classes
    BusIfBase
    Annotations
    @deprecated
    Deprecated

    (Since version 2024.12.30) readError rename to bus_rderr

Inherited from Serializable

Inherited from Serializable

Inherited from Product

Inherited from Equals

Inherited from BusIf

Inherited from BusIfBase

Inherited from Area

Inherited from OverridedEqualsHashCode

Inherited from ValCallbackRec

Inherited from ValCallback

Inherited from NameableByComponent

Inherited from Nameable

Inherited from ContextUser

Inherited from ScalaLocated

Inherited from GlobalDataUser

Inherited from OwnableRef

Inherited from AnyRef

Inherited from Any

Ungrouped