case class SpiXdrMaster(p: SpiXdrParameter) extends Bundle with IMasterSlave with Product with Serializable
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- By Inheritance
- SpiXdrMaster
- Serializable
- Serializable
- Product
- Equals
- IMasterSlave
- Bundle
- ValCallbackRec
- ValCallback
- MultiData
- Data
- InComponent
- OverridedEqualsHashCode
- SpinalTagReady
- Assignable
- NameableByComponent
- Nameable
- OwnableRef
- ContextUser
- ScalaLocated
- GlobalDataUser
- AnyRef
- Any
- Hide All
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- Public
- All
Instance Constructors
- new SpiXdrMaster(p: SpiXdrParameter)
Type Members
-
abstract
type
RefOwnerType
- Definition Classes
- OwnableRef
- case class SpiIce40(p: SpiXdrParameter) extends Bundle with Product with Serializable
Value Members
-
def
##(right: Data): Bits
Concatenation between two signals
Concatenation between two signals
- Definition Classes
- Data
-
def
#*(count: Int): Bits
Return the
count
time concatenation of the signal.Return the
count
time concatenation of the signal.- Definition Classes
- Data
-
def
IFparent: Data
- Definition Classes
- Data
-
val
_spinalTags: LinkedHashSet[SpinalTag]
- Definition Classes
- SpinalTagReady
-
def
addAttribute(attribute: Attribute): SpiXdrMaster.this.type
- Definition Classes
- Data → SpinalTagReady
-
def
addAttribute(name: String, value: Int): SpiXdrMaster.this.type
- Definition Classes
- SpinalTagReady
-
def
addAttribute(name: String, value: String): SpiXdrMaster.this.type
- Definition Classes
- SpinalTagReady
-
def
addAttribute(name: String): SpiXdrMaster.this.type
- Definition Classes
- SpinalTagReady
-
def
addTag[T <: SpinalTag](spinalTag: T): SpiXdrMaster.this.type
- Definition Classes
- MultiData → SpinalTagReady
-
def
addTags(h: SpinalTag, tail: SpinalTag*): SpiXdrMaster.this.type
- Definition Classes
- SpinalTagReady
-
def
addTags[T <: SpinalTag](tags: Iterable[T]): SpiXdrMaster.this.type
- Definition Classes
- SpinalTagReady
-
def
allowDirectionLessIo(): SpiXdrMaster.this.type
Allow a signal of an io
Bundle
to be directionless.Allow a signal of an io
Bundle
to be directionless.- Definition Classes
- Data
- See also
-
def
allowOverride(): SpiXdrMaster.this.type
Allow a signal to be overridden.
Allow a signal to be overridden.
- Definition Classes
- Data
- See also
-
def
allowPartialyAssigned(): SpiXdrMaster.this.type
Allow a register to be partially assigned
Allow a register to be partially assigned
- Definition Classes
- Data
-
def
allowPruning(): SpiXdrMaster.this.type
- Definition Classes
- Data
-
def
allowSimplifyIt(): SpiXdrMaster.this.type
- Definition Classes
- Data
-
def
allowUnsetRegToAvoidLatch(): SpiXdrMaster.this.type
Allow a register to have only an init (no assignments)
Allow a register to have only an init (no assignments)
- Definition Classes
- Data
- See also
-
def
as[T <: Data](dataType: HardType[T]): T
- Definition Classes
- Data
-
def
asBits: Bits
Cast signal to Bits
-
def
asData: Data
- Definition Classes
- Data
-
def
asInOut(): SpiXdrMaster.this.type
Set a signal as
inout
-
def
asInput(): SpiXdrMaster.this.type
Set a data as input
-
def
asOutput(): SpiXdrMaster.this.type
Set a data as output
-
def
assignAllByName(that: Bundle): Unit
Assign the bundle with an other bundle by name
Assign the bundle with an other bundle by name
- Definition Classes
- Bundle
-
def
assignDontCare(): SpiXdrMaster.this.type
Assign the default 'x' value to all signals composing this type.
Assign the default 'x' value to all signals composing this type.
- Definition Classes
- Data
- See also
-
def
assignDontCareToUnasigned(): SpiXdrMaster.this.type
- Definition Classes
- Data
- def assignFormalRandom(kind: RandomExpKind): Unit
-
final
def
assignFrom(that: AnyRef, target: AnyRef = this)(implicit loc: Location): Unit
- Definition Classes
- Data
- def assignFromBits(bits: Bits, hi: Int, lo: Int): Unit
- def assignFromBits(bits: Bits): Unit
-
def
assignFromBits(bits: Bits, offset: Int, bitCount: BitCount): Unit
- Definition Classes
- Data
-
def
assignSomeByName(that: Bundle): Unit
Assign all possible signal fo the bundle with an other bundle by name
Assign all possible signal fo the bundle with an other bundle by name
- Definition Classes
- Bundle
-
def
assignUnassignedByName(that: MultiData): Unit
- Definition Classes
- MultiData
-
def
bundleAssign(that: Bundle)(f: (Data, Data) ⇒ Unit): Unit
- Definition Classes
- Bundle
-
def
checkDir(that: Bundle): Boolean
for interface find modport
for interface find modport
- Definition Classes
- Bundle
-
def
clearAll(): SpiXdrMaster.this.type
Clear all bits to
and return itselfFalse
Clear all bits to
and return itselfFalse
- Definition Classes
- Data
-
def
clone(): SpiXdrMaster
- Definition Classes
- SpiXdrMaster → Bundle → Data → AnyRef
-
def
component: Component
- Definition Classes
- ContextUser
-
final
def
compositAssignFrom(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit
- Definition Classes
- Assignable
-
val
compositeAssign: Assignable
- Definition Classes
- Assignable
- def copyDirectionOfImpl(that: Data): SpiXdrMaster.this.type
- val data: Vec[XdrPin]
- def decode(sel: Bool, ss: Seq[Bool]): SpiXdrMaster
- def decode(ssId: Int, activeLow: Boolean = true): SpiXdrMaster
-
def
dirString(): String
- Definition Classes
- Data
-
def
dontSimplifyIt(): SpiXdrMaster.this.type
- Definition Classes
- Data
- def elements: ArrayBuffer[(String, Data)]
-
var
elementsCache: ArrayBuffer[(String, Data)]
- Definition Classes
- Bundle
-
def
elementsString: String
- Definition Classes
- MultiData
-
def
equals(obj: Any): Boolean
- Definition Classes
- OverridedEqualsHashCode → AnyRef → Any
-
def
existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean
- Definition Classes
- SpinalTagReady
-
def
filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]
- Definition Classes
- SpinalTagReady
-
def
find(name: String): Data
- Definition Classes
- MultiData
-
def
findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]
- Definition Classes
- SpinalTagReady
- def flatten: Seq[BaseType]
- def flattenForeach(body: (BaseType) ⇒ Unit): Unit
- def flattenLocalName: Seq[String]
-
def
flip(): SpiXdrMaster.this.type
Flip the direction of the signal.
-
def
foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit
- Definition Classes
- Nameable
-
def
foreachTag(body: (SpinalTag) ⇒ Unit): Unit
- Definition Classes
- SpinalTagReady
- def freeze(): SpiXdrMaster.this.type
-
def
getAheadValue(): SpiXdrMaster.this.type
For a register, get the value it will have at the next clock, as a combinational signal.
For a register, get the value it will have at the next clock, as a combinational signal.
- Definition Classes
- Data
-
def
getBitsWidth: Int
Return the width of the data
-
def
getComponent(): Component
- Definition Classes
- Data → InComponent → NameableByComponent
-
def
getComponents(): Seq[Component]
Get current component with all parents
Get current component with all parents
- Definition Classes
- InComponent
-
def
getDirection: IODirection
- Definition Classes
- Data
-
def
getDisplayName(): String
- Definition Classes
- Nameable
-
def
getInstanceCounter: Int
- Definition Classes
- ContextUser
-
def
getMuxType[T <: Data](list: TraversableOnce[T]): HardType[T]
- Definition Classes
- Data
-
def
getName(default: String): String
- Definition Classes
- NameableByComponent → Nameable
-
def
getName(): String
- Definition Classes
- NameableByComponent → Nameable
-
def
getPartialName(): String
- Definition Classes
- Nameable
-
def
getPath(from: Component, to: Component): Seq[Component]
- Definition Classes
- NameableByComponent
-
def
getRealSource: Any
- Definition Classes
- Assignable
-
def
getRealSourceNoRec: Any
- Definition Classes
- Data → Assignable
-
def
getRefOwnersChain(): List[Any]
- Definition Classes
- OwnableRef
-
def
getRootParent: Data
- Definition Classes
- Data
-
def
getRtlPath(separator: String = "/"): String
- Definition Classes
- Data
-
def
getScalaLocationLong: String
- Definition Classes
- ScalaLocated
-
def
getScalaLocationShort: String
- Definition Classes
- ScalaLocated
-
def
getScalaTrace(): Throwable
- Definition Classes
- ScalaLocated
-
def
getTag[T <: SpinalTag](clazz: Class[T]): Option[T]
- Definition Classes
- SpinalTagReady
-
def
getTags(): LinkedHashSet[SpinalTag]
- Definition Classes
- SpinalTagReady
-
def
getTagsOf[T <: SpinalTag]()(implicit tag: ClassTag[T]): Iterable[T]
- Definition Classes
- SpinalTagReady
-
def
getTypeString: String
- Definition Classes
- Bundle
-
def
getZero: SpiXdrMaster.this.type
Create a signal set to 0
-
val
globalData: GlobalData
- Definition Classes
- GlobalDataUser
-
var
hardtype: HardType[_]
- Definition Classes
- Bundle
-
def
hasTag[T <: SpinalTag](clazz: Class[T]): Boolean
- Definition Classes
- SpinalTagReady
-
def
hasTag(spinalTag: SpinalTag): Boolean
- Definition Classes
- SpinalTagReady
-
def
hashCode(): Int
- Definition Classes
- OverridedEqualsHashCode → AnyRef → Any
-
final
def
initFrom(that: AnyRef, target: AnyRef = this): Unit
- Definition Classes
- Data
-
def
instanceAttributes(language: Language): Iterable[Attribute]
- Definition Classes
- SpinalTagReady
-
def
instanceAttributes: Iterable[Attribute]
- Definition Classes
- SpinalTagReady
-
final
def
intoMaster(): SpiXdrMaster.this.type
Convert into master
Convert into master
- Definition Classes
- IMasterSlave
-
final
def
intoSlave(): SpiXdrMaster.this.type
Convert into slave
Convert into slave
- Definition Classes
- IMasterSlave
-
def
isAnalog: Boolean
- Definition Classes
- Data
-
def
isComb: Boolean
- Definition Classes
- Data
-
def
isCompletelyUnnamed: Boolean
- Definition Classes
- Nameable
-
def
isDirectionLess: Boolean
- Definition Classes
- Data
-
def
isEmptyOfTag: Boolean
- Definition Classes
- SpinalTagReady
-
def
isInOut: Boolean
- Definition Classes
- Data
-
def
isInput: Boolean
- Definition Classes
- Data
-
def
isInputOrInOut: Boolean
- Definition Classes
- Data
-
final
def
isMasterInterface: Boolean
Are port directions set for a Master interface?
Are port directions set for a Master interface?
- Definition Classes
- IMasterSlave
-
final
def
isNamed: Boolean
- Definition Classes
- Nameable
-
def
isOutput: Boolean
- Definition Classes
- Data
-
def
isOutputOrInOut: Boolean
- Definition Classes
- Data
-
def
isPriorityApplicable(namePriority: Byte): Boolean
- Definition Classes
- Nameable
-
def
isReg: Boolean
- Definition Classes
- Data
-
def
isRegOnAssign: Boolean
- Definition Classes
- Data
-
final
def
isSlaveInterface: Boolean
Are port directions set for a Master interface?
Are port directions set for a Master interface?
- Definition Classes
- IMasterSlave
-
def
isUnnamed: Boolean
- Definition Classes
- NameableByComponent → Nameable
- def lazySclk(ssIdle: Int, sclkValue: Boolean): SpiXdrMaster
-
val
name: String
- Definition Classes
- Nameable
-
def
noBackendCombMerge(): SpiXdrMaster.this.type
Put the combinatorial logic driving this signal in a separate process
Put the combinatorial logic driving this signal in a separate process
- Definition Classes
- Data
-
def
noCombLoopCheck(): SpiXdrMaster.this.type
Disable combinatorial loop checking for this Data
Disable combinatorial loop checking for this Data
- Definition Classes
- Data
- See also
-
def
onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit
- Definition Classes
- SpinalTagReady
-
def
overrideLocalName(name: String): SpiXdrMaster.this.type
- Definition Classes
- Nameable
- val p: SpiXdrParameter
-
val
parent: Data
- Definition Classes
- Data
-
val
parentScope: ScopeStatement
- Definition Classes
- ContextUser
-
def
pull(propagateName: Boolean): SpiXdrMaster.this.type
- Definition Classes
- Data
-
def
pull(): SpiXdrMaster.this.type
Pull a signal to the top level (use for debugging)
Pull a signal to the top level (use for debugging)
- Definition Classes
- Data
-
def
purify(): SpiXdrMaster.this.type
- Definition Classes
- Data
-
def
randBoot(u: Unit): SpiXdrMaster.this.type
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)
- Definition Classes
- Data
-
val
refOwner: RefOwnerType
- Definition Classes
- OwnableRef
- Annotations
- @DontName()
-
def
reflectNames(): Unit
- Definition Classes
- Nameable
-
def
removeAssignments(data: Boolean = true, init: Boolean = true, initial: Boolean = true): SpiXdrMaster.this.type
- Definition Classes
- Data
-
def
removeDataAssignments(): SpiXdrMaster.this.type
- Definition Classes
- Data
-
def
removeInitAssignments(): SpiXdrMaster.this.type
- Definition Classes
- Data
-
def
removeTag(spinalTag: SpinalTag): SpiXdrMaster.this.type
- Definition Classes
- SpinalTagReady
-
def
removeTags(tags: Iterable[SpinalTag]): SpiXdrMaster.this.type
- Definition Classes
- SpinalTagReady
-
def
resized: SpiXdrMaster.this.type
Return a version of the signal which is allowed to be automatically resized where needed.
Return a version of the signal which is allowed to be automatically resized where needed.
The resize operation is deferred until the point of assignment later. The resize may widen or truncate, retaining the LSB.
- Definition Classes
- Data
- See also
-
def
rootIF(): Interface
root interface
root interface
- Definition Classes
- Data
-
def
rootIFList(): List[Interface]
- Definition Classes
- Data
-
def
rootIFrec(now: Data, lastRoot: List[Interface]): List[Interface]
- Definition Classes
- Data
-
val
scalaTrace: Throwable
- Definition Classes
- ScalaLocated
- val sclk: XdrOutput
-
def
setAll(): SpiXdrMaster.this.type
Set all bits to
and return itselfTrue
Set all bits to
and return itselfTrue
- Definition Classes
- Data
-
def
setAsAnalog(): SpiXdrMaster.this.type
- Definition Classes
- Data
-
def
setAsComb(): SpiXdrMaster.this.type
Set baseType to Combinatorial
-
def
setAsDirectionLess(): SpiXdrMaster.this.type
Remove the direction (
in
,out
,inout
) to a signal -
final
def
setAsMaster(): Unit
Set as master interface
Set as master interface
- Definition Classes
- IMasterSlave
-
def
setAsReg(): SpiXdrMaster.this.type
Set baseType to reg
-
final
def
setAsSlave(): Unit
Set a slave interface
Set a slave interface
- Definition Classes
- IMasterSlave
-
def
setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, postfix: String): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, namePriority: Byte): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, weak: Boolean): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setName(name: String, namePriority: Byte): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setName(name: String, weak: Boolean): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setName(name: String): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setNameAsWeak(): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setOutputAsReg(): SpiXdrMaster.this.type
Recursively set baseType to reg only for output
Recursively set baseType to reg only for output
- Definition Classes
- Data
-
def
setPartialName(name: String, namePriority: Byte, owner: Any): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String, namePriority: Byte): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String, weak: Boolean): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String, namePriority: Byte): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String, weak: Boolean): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
setRefOwner(that: Any): Unit
- Definition Classes
- OwnableRef
-
def
setScalaLocated(source: ScalaLocated): SpiXdrMaster.this.type
- Definition Classes
- ScalaLocated
-
def
setWeakName(name: String): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
spinalTags: LinkedHashSet[SpinalTag]
- Definition Classes
- SpinalTagReady
- val ss: Bits
-
def
toIo(): SpiXdrMaster.this.type
- Definition Classes
- Data
- def toMdio(): Mdio
-
def
toMuxInput[T <: Data](muxOutput: T): T
- Definition Classes
- Data
- def toSpi(): SpiHalfDuplexMaster
- def toSpiEcp5(): SpiMaster
- def toSpiEcp5Flash(): SpiMaster
- def toSpiIce40(): SpiIce40
- def toString(): String
- def unfreeze(): SpiXdrMaster.this.type
-
def
unsetName(): SpiXdrMaster.this.type
- Definition Classes
- Nameable
-
def
valCallback[T](ref: T, name: String): T
- Definition Classes
- ValCallbackRec → ValCallback
-
def
valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit
- Definition Classes
- ValCallbackRec
-
def
valCallbackRec(ref: Any, name: String): Unit
- Definition Classes
- Bundle → ValCallbackRec
- def withoutSs(): SpiXdrMaster
-
def
wrapNext(): SpiXdrMaster.this.type
- Definition Classes
- Data
-
def
zipByName(that: MultiData, rec: ArrayBuffer[(BaseType, BaseType)] = ArrayBuffer()): ArrayBuffer[(BaseType, BaseType)]
- Definition Classes
- MultiData
Deprecated Value Members
-
def
asDirectionLess(): SpiXdrMaster.this.type
- Definition Classes
- Data
- Annotations
- @deprecated
- Deprecated
(Since version ???) use setAsDirectionLess instead
-
def
asMaster(): Unit
Override it to define port directions for a master interface.
Override it to define port directions for a master interface.
- Definition Classes
- SpiXdrMaster → IMasterSlave
- Deprecated
This method must be overriden but not called. Calling this method is not correct. Call
setAsMaster()
orintoMaster()
instead. This method is namedasXxx
but it does not returnXxx
. This method does not updateisMasterInterface
andisSlaveInterface
.
-
def
asSlave(): Unit
Override it to define port directions for a master interface.
Override it to define port directions for a master interface.
If not overriden, defaults to the opposite port directions of
asMaster()
.- Definition Classes
- IMasterSlave
- Deprecated
This method can be overriden but not called. Calling this method is not correct. Call
setAsSlave()
orintoSlave()
instead. This method is namedasXxx
but it does not returnXxx
. This method does not updateisMasterInterface
andisSlaveInterface
.
-
def
genIf(cond: Boolean): SpiXdrMaster.this.type
Generate this if condition is true
Generate this if condition is true
- Definition Classes
- Data
- Annotations
- @deprecated
- Deprecated
does not work with <>, use 'someBool generate Type()' or 'if(condition) Type() else null' instead