case class SdramConfig(generation: SdramGeneration, bankWidth: Int, columnWidth: Int, rowWidth: Int, dataWidth: Int, ddrMHZ: Int, ddrWrLat: Int, ddrRdLat: Int, sdramtime: SdramTiming) extends Product with Serializable
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Instance Constructors
- new SdramConfig(generation: SdramGeneration, bankWidth: Int, columnWidth: Int, rowWidth: Int, dataWidth: Int, ddrMHZ: Int, ddrWrLat: Int, ddrRdLat: Int, sdramtime: SdramTiming)
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def
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- def bankCount: Int
- val bankWidth: Int
- def burstLength: Int
- def byteAddressWidth: Int
- def bytePerWord: Int
- def capacity: BigInt
- def chipAddressWidth: Int
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def
clone(): AnyRef
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- @throws( ... ) @native() @IntrinsicCandidate()
- def columnSize: Int
- val columnWidth: Int
- def cycleTime_ns: Int
- val dataWidth: Int
- val ddrMHZ: Int
- val ddrRdLat: Int
- def ddrStartdelay: Int
- val ddrWrLat: Int
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final
def
eq(arg0: AnyRef): Boolean
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- val generation: SdramGeneration
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final
def
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- def rowSize: Int
- val rowWidth: Int
- val sdramtime: SdramTiming
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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- def tFAW: Int
- def tPhyWrlat: Int
- def tRAS: Int
- def tRCD: Int
- def tREF: Int
- def tRFC: Int
- def tRP: Int
- def tRRD: Int
- def tRTP: Int
- def tRTW: Int
- def tRddataEn: Int
- def tWR: Int
- def tWTR: Int
- def timeCycle(time: Int, cycTime: Int): Int
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- def wordAddressWidth: Int
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