abstract class DmaSgTester extends AnyRef
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Instance Constructors
- new DmaSgTester(p: Parameter, clockDomain: ClockDomain, inputsIo: Seq[Bsb], outputsIo: Seq[Bsb], interruptsIo: Bits, memory: SparseMemory, dut: Core[_])
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final
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final
def
##(): Int
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final
def
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- def allowWrite(address: Long): Unit
- def allowWrite(address: Long, value: Byte): Unit
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final
def
asInstanceOf[T0]: T0
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- val channelAgent: Seq[SimThread]
- def channelBusy(channel: Int): Boolean
- def channelConfig(channel: Int, fifoBase: Int, fifoBytes: Int, priority: Int, weight: Int): Unit
- def channelInterruptConfigure(channel: Int, mask: Int): Unit
- def channelPopMemory(channel: Int, address: BigInt, bytePerBurst: Int): Unit
- def channelPopStream(channel: Int, portId: Int, sourceId: Int, sinkId: Int, withLast: Boolean): Unit
- def channelProgress(channel: Int): Int
- def channelPushMemory(channel: Int, address: BigInt, bytePerBurst: Int): Unit
- def channelPushStream(channel: Int, portId: Int, sourceId: Int, sinkId: Int, completionOnPacket: Boolean = false): Unit
- def channelSgBusy(channel: Int): Boolean
- def channelStart(channel: Int, bytes: BigInt, selfRestart: Boolean): Unit
- def channelStartAndWait(channel: Int, bytes: BigInt, doCount: Int): Unit
- def channelStartSg(channel: Int, head: Long): Unit
- def channelStop(channel: Int): Unit
- def channelToAddress(channel: Int): Int
- def channelWaitCompletion(channel: Int): Unit
- def channelWaitSgDone(channel: Int): Unit
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def
clone(): AnyRef
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- protected[lang]
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- @throws( ... ) @native() @IntrinsicCandidate()
- def ctrlRead(address: BigInt): BigInt
- def ctrlWrite(data: BigInt, address: BigInt): Unit
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final
def
eq(arg0: AnyRef): Boolean
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equals(arg0: Any): Boolean
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final
def
getClass(): Class[_]
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def
hashCode(): Int
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- val inputs: IndexedSeq[AnyRef { ... /* 5 definitions in type refinement */ }]
- val inputsTrasher: Any
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final
def
isInstanceOf[T0]: Boolean
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- def log(that: String): Unit
- val memoryReserved: MemoryRegionAllocator
- val mutex: SimMutex
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final
def
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def
notify(): Unit
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final
def
notifyAll(): Unit
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- @native() @IntrinsicCandidate()
- val outputs: IndexedSeq[AnyRef { ... /* 4 definitions in type refinement */ }]
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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def
toString(): String
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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final
def
wait(): Unit
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- @throws( ... )
- def waitCompletion(): Unit
- def writeDescriptor(address: Long, push: Long, pop: Long, size: Long, next: Long, completed: Boolean, m2sLast: Boolean = false): Unit
- def writeNotification(address: Long, value: Byte): Unit
- def writeTail(address: Long): Unit
- val writesAllowed: HashMap[Long, (Byte, Int, Boolean)]
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finalize(): Unit
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