- About SpinalHDL
- Getting Started
- Data types
- Sequential logic
- Design errors
- Other language features
- Developers area
Welcome to SpinalHDL’s documentation!¶
Site purpose and structure¶
This site presents the SpinalHDL language and how to use it on concrete examples.
If you are learning the language from scratch, this presentation is probably a good starting point.
What is SpinalHDL ?¶
SpinalHDL is an open source high-level hardware description language. It can be used as an alternative to VHDL or Verilog and has several advantages over them.
Also, SpinalHDL is not an HLS approach. Its goal is not to push something abstract into flip-flops and gates, but by using simple elements (flip-flops, gates, if / case statments) create a new abstraction level and help the designer to reuse their code and not write the same thing over and over again.
SpinalHDL is fully interoperable with standard VHDL/Verilog-based EDA tools (simulators and synthetizers) as the output generated by the toolchain could be VHDL or Verilog. It also enables mixed designs where SpinalHDL components inter-operate with VHDL or Verilog IPs.
Advantages of using SpinalHDL over VHDL / Verilog¶
As SpinalHDL is based on a high-level language, it provides several advantages to improve your hardware coding:
No more endless wiring - Create and connect complex buses like AXI in one single line.
Evolving capabilities - Create your own bus definitions and abstraction layers.
Reduce code size - By a high factor, especially for wiring. This enables you to have a better overview of your code base, increase your productivity and create fewer headaches.
Free and user friendly IDE - Thanks to Scala tools for auto-completion, error highlighting, navigation shortcuts, and many others.
Powerful and easy type conversions - Bidirectional translation between any data type and bits. Useful when loading a complex data structure from a CPU interface.
Loop detection - Tools check that there are no combinatorial loops / latches.
Clock domain safety - The tools inform you that there are no unintentional clock domain crossings.
Generic design - There are no restrictions to the genericity of your hardware description by using Scala constructs.
SpinalHDL uses two licenses, one for spinal.core, and one for spinal.lib.
spinal.core (the compiler) is under the LGPL license, which could be summarized with following statements:
You can make money with your SpinalHDL description and its generated RTL.
You don’t have to share your SpinalHDL description and its generated RTL.
There are no fees and no royalties.
If your make improvements to the SpinalHDL core, please share your modifications to make the tool better for everybody.
spinal.lib (a general purpose library of components/tools/interfaces) is under the permissive MIT license.