SpinalHDL

About SpinalHDL
Getting Started
Data types
- Bool
  - Description
  - Declaration
  - Operators
    - Logic
    - Edge detection
    - Comparison
    - Type cast
    - Misc
- Bits
  - Description
  - Declaration
  - Operators
    - Logic
    - Comparison
    - Type cast
    - Bit extraction
    - Misc
- UInt/SInt
- SpinalEnum
  - Description
  - Declaration
    - Encoding
    - Example
  - Operators
    - Comparison
    - Type cast
- Bundle
- Vec
  - Description
  - Declaration
    - Examples
  - Operators
- UFix/SFix
- Floating
- Introduction
Structuring
Semantic
Sequential logic
- Registers
- RAM/ROM
Design errors
Other language features
Libraries
Simulation
Examples
Legacy
- RiscV
- pinsec
Developers area

SpinalHDL

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Users
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Users¶

Companies¶

QsPin, Belgium

Repositories¶

J1Sc Stack CPU
VexRiscv CPU and SoC

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Other Versions v: v1.6.0

Tags: v1.3.1; v1.3.8; v1.5.0; v1.6.0; v1.8.0

Branches: dev; master

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