case class AxiLite4Master(axil: AxiLite4, clockDomain: ClockDomain) extends Product with Serializable
Simulation master for the AxiLite4 bus protocol spinal.lib.bus.amba4.axilite.AxiLite4.
- axil
bus master to drive
- clockDomain
clock domain to sample data on
SimConfig.compile(new Component { val io = new Bundle { val axil = slave(AxiLite4(AxiLite4Config(addressWidth = 32, dataWidth = 32))) } }).doSim("sample") { dut => val master = AxiLite4Master(dut.io.axil, dut.clockDomain) val data = master.read(0x1000, 4) }
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new
AxiLite4Master(axil: AxiLite4, clockDomain: ClockDomain)
create a new simulation master with the bus instance and clock domain.
create a new simulation master with the bus instance and clock domain.
- axil
bus master to drive
- clockDomain
clock domain to sample data on
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asInstanceOf[T0]: T0
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- val axil: AxiLite4
- val clockDomain: ClockDomain
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def
read(address: BigInt, totalBytes: BigInt): List[Byte]
Read synchronously multiple bytes from the specified address.
Read synchronously multiple bytes from the specified address.
- address
address to read from, does not need to be aligned (data will be truncated automatically)
- totalBytes
total number of bytes in the result
- returns
read data
- Note
The bus master will automatically issue multiple transactions if more than one is needed, due to address alignment or length.
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def
readCB(address: BigInt, totalBytes: BigInt)(callback: (List[Byte]) ⇒ Unit): Unit
Read asynchronously multiple bytes.
Read asynchronously multiple bytes. Same semantics as read, but result is delivered in the callback
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def
readIdle: Boolean
check if all read channels are idle
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def
readSingle(address: BigInt)(callback: (List[Byte]) ⇒ Unit): Unit
Read asynchronously one beat of bus data width.
Read asynchronously one beat of bus data width. Address must be aligned
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def
reset(): Unit
Reset bus master and drop all pending transactions
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def
write(addr: BigInt, data: List[Byte]): Unit
Write synchronously multiple bytes to the specified address.
Write synchronously multiple bytes to the specified address.
- addr
address to write to; does not need to be aligned (data will be padded automatically)
- data
list of bytes to write to the address. When longer than the bus width, multiple transactions will be issued
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def
writeCB(addr: BigInt, data: List[Byte])(callback: ⇒ Unit): Unit
Same as
write
, but asynchronously -
def
writeIdle: Boolean
check if all write channels are idle
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def
writeSingle(addr: BigInt, data: List[Byte])(callback: ⇒ Unit): Unit
Write a single transaction.
Write a single transaction. Address must be aligned
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