Packages

package sim

Type Members

  1. case class AxiLite4Driver(axi: AxiLite4, clockDomain: ClockDomain) extends Product with Serializable
  2. case class AxiLite4Master(axil: AxiLite4, clockDomain: ClockDomain) extends Product with Serializable

    Simulation master for the AxiLite4 bus protocol spinal.lib.bus.amba4.axilite.AxiLite4.

    Simulation master for the AxiLite4 bus protocol spinal.lib.bus.amba4.axilite.AxiLite4.

    axil

    bus master to drive

    clockDomain

    clock domain to sample data on

    Example: 

    1. SimConfig.compile(new Component {
  val io = new Bundle {
    val axil = slave(AxiLite4(AxiLite4Config(addressWidth = 32, dataWidth = 32)))
  }
}).doSim("sample") { dut =>
  val master = AxiLite4Master(dut.io.axil, dut.clockDomain)
  val data = master.read(0x1000, 4)
}
  3. abstract class AxiLite4ReadOnlyMonitor extends AnyRef
  4. class AxiLite4ReadOnlySlaveAgent extends AnyRef
  5. abstract class AxiLite4WriteOnlyMonitor extends AnyRef
  6. class AxiLite4WriteOnlySlaveAgent extends AnyRef

Ungrouped