case class Axi4StreamSlave(axis: Axi4Stream, clockDomain: ClockDomain) extends Product with Serializable
Simulation slave for the Axi4Stream bus protocol Axi4Stream.
- axis
bus slave to drive
- clockDomain
clock domain to sample data on
SimConfig.compile(new Component { val io = new Bundle { val axisMaster = master(Axi4Stream(Axi4StreamConfig(32))) } io.axisMaster.assignDontCare }).doSim("sample") { dut => val slave = Axi4StreamSlave(dut.io.axisMaster, dut.clockDomain) val data = slave.recv() }
- Note
The current implementation does not buffer unexpected transactions (i.e. bus activity when no
recv
has been issued). In some race conditions, this may result in incomplete captures due to the first beats being lost. Consider enqueuing a asynchronous request with the callback interface (recvCB
) before issuing the triggering action.
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Axi4StreamSlave(axis: Axi4Stream, clockDomain: ClockDomain)
create a simulation slave with the given bus instance and clock domain
create a simulation slave with the given bus instance and clock domain
- axis
bus slave to drive
- clockDomain
clock domain to sample data on
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- val axis: Axi4Stream
- val clockDomain: ClockDomain
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def
recv(): List[Byte]
Receive synchronously a full transaction from the bus.
-
def
recvCB()(callback: (List[Byte]) ⇒ Unit): Unit
Receive asynchronously; same as
recv
, but result is delivered in a callback -
def
reset(): Unit
Reset bus slave (dropping all pending transactions)
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