Packages

  • package root
    Definition Classes
    root
  • package vexiiriscv
    Definition Classes
    root
  • package memory
    Definition Classes
    vexiiriscv
  • class MmuPlugin extends FiberPlugin with AddressTranslationService

    Implement the RISC-V MMU using a N-way set associative TLB storage.

    Implement the RISC-V MMU using a N-way set associative TLB storage. This fit very well with FPGA which have distributed memories. For FPGA that do not have that, the MmuPortParameter can be configured to have a low number of sets or use 1 cycle delay to be inferable as block ram.

    Plugins which uses the MmuPlugin can request TLB storage, then they can require the MmuPlugin to bind a new port on a existing pipeline using that TLB storage. A given TLB storage can be used by multiple MMU ports.

    MMU miss will not by itself trigger a TLB refill. This is instead triggered by the TrapPlugin.

    Definition Classes
    memory
  • PortSpec
  • RefOwnerType
  • StorageSpec

case class PortSpec(stages: Seq[NodeBaseApi], preAddress: Payload[UInt], forcePhysical: Payload[Bool], usage: AddressTranslationPortUsage, pp: MmuPortParameter, ss: StorageSpec, rsp: AddressTranslationRsp) extends Product with Serializable

Linear Supertypes
Serializable, Serializable, Product, Equals, AnyRef, Any
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  1. PortSpec
  2. Serializable
  3. Serializable
  4. Product
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Visibility
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Instance Constructors

  1. new PortSpec(stages: Seq[NodeBaseApi], preAddress: Payload[UInt], forcePhysical: Payload[Bool], usage: AddressTranslationPortUsage, pp: MmuPortParameter, ss: StorageSpec, rsp: AddressTranslationRsp)

Value Members

  1. val ctrlStage: NodeBaseApi
  2. val forcePhysical: Payload[Bool]
  3. val hitsStage: NodeBaseApi
  4. val pp: MmuPortParameter
  5. val preAddress: Payload[UInt]
  6. val readStage: NodeBaseApi
  7. val rsp: AddressTranslationRsp
  8. val rspStage: NodeBaseApi
  9. val ss: StorageSpec
  10. val stages: Seq[NodeBaseApi]
  11. val usage: AddressTranslationPortUsage