Type Members

1.  case class AddressTranslationInvalidation() extends Bundle with Product with Serializable

   Used by the TrapPlugin to ask the MmuPlugin to invalidate its TLB (on sfence.vma / satp updates)

2.  case class AddressTranslationInvalidationCmd() extends Bundle with Product with Serializable
3.  trait AddressTranslationPortUsage extends AnyRef
4.  case class AddressTranslationRefill(storageWidth: Int) extends Bundle with Product with Serializable

   Interface used by the TrapPlugin to ask the MMU's page walker to do work

5.  case class AddressTranslationRefillCmd(storageWidth: Int) extends Bundle with Product with Serializable
6.  case class AddressTranslationRefillRsp() extends Bundle with Product with Serializable
7.  class AddressTranslationRsp extends Area
8.  trait AddressTranslationService extends Area

   Implemented by the MmuPlugin, allows other plugins to create new address translation interfaces

9.  case class DBusAccess(refillCount: Int) extends Bundle with Product with Serializable
10.  case class DBusAccessCmd() extends Bundle with Product with Serializable
11.  case class DBusAccessRsp(refillCount: Int) extends Bundle with Product with Serializable
12.  trait DBusAccessService extends AnyRef
13.  case class MmuEntryFlags() extends Bundle with Product with Serializable
14.  case class MmuLevel(virtualWidth: Int, physicalWidth: Int, virtualOffset: Int, physicalOffset: Int, entryOffset: Int) extends Product with Serializable
15.  class MmuPlugin extends FiberPlugin with AddressTranslationService

    Implement the RISC-V MMU using a N-way set associative TLB storage.

    Implement the RISC-V MMU using a N-way set associative TLB storage. This fit very well with FPGA which have distributed memories. For FPGA that do not have that, the MmuPortParameter can be configured to have a low number of sets or use 1 cycle delay to be inferable as block ram.

    Plugins which uses the MmuPlugin can request TLB storage, then they can require the MmuPlugin to bind a new port on a existing pipeline using that TLB storage. A given TLB storage can be used by multiple MMU ports.

    MMU miss will not by itself trigger a TLB refill. This is instead triggered by the TrapPlugin.

16.  case class MmuPortParameter(readAt: Int, hitsAt: Int, ctrlAt: Int, rspAt: Int) extends Product with Serializable
17.  case class MmuSpec(levels: Seq[MmuLevel], entryBytes: Int, virtualWidth: Int, physicalWidth: Int, satpMode: Int, pteReserved: BigInt) extends Product with Serializable
18.  case class MmuStorageLevel(id: Int, ways: Int, sets: Int) extends Product with Serializable
19.  case class MmuStorageParameter(levels: Seq[MmuStorageLevel], priority: Int) extends Product with Serializable
20.  class PmaCmd extends Bundle
21.  class PmaLogic extends Area

    Implement the hardware to translate an address into its Physical Memory Access permitions.

    Implement the hardware to translate an address into its Physical Memory Access permitions. For VexiiRiscv the permitions are : - fault => is there something at that address ? - io => is it an IO memory region (strongly ordered / with side effects) ?

22.  trait PmaOp extends AnyRef
23.  case class PmaPort(addressWidth: Int, sizes: Seq[Int], ops: Seq[PmaOp]) extends Bundle with Product with Serializable
24.  class PmaRsp extends Bundle
25.  case class PmpParam(pmpSize: Int, granularity: Int, withTor: Boolean = true, withNapot: Boolean = true) extends Product with Serializable
26.  class PmpPlugin extends FiberPlugin with PmpService

    This PMP implementation is quite regular, but allows the user to get ports which are pipelined (to improve FMax / timings)

27.  case class PmpPortParameter(napotMatchAt: Int, napotHitsAt: Int, torCmpAt: Int, torHitsAt: Int, hitsAt: Int, rspAt: Int) extends Product with Serializable
28.  class PmpRsp extends Area
29.  trait PmpService extends Area
30.  case class PmpStorageParameter(slots: Int) extends Product with Serializable

    Reading the RISC-V spec to figure out all the flags/details of the PMP is just too tricky.

    Reading the RISC-V spec to figure out all the flags/details of the PMP is just too tricky. A good way to figure things out is to loook at spike (software implementation) : - https://github.com/riscv-software-src/riscv-isa-sim/blob/2c67071743d4b55719cee22fdb319df2a0756db7/riscv/mmu.cc#L348 - https://github.com/riscv-software-src/riscv-isa-sim/blob/2c67071743d4b55719cee22fdb319df2a0756db7/riscv/csrs.cc#L183 - https://github.com/riscv-software-src/riscv-isa-sim/blob/2c67071743d4b55719cee22fdb319df2a0756db7/riscv/mmu.cc#L348

    In particular, one tricky thing with the PMP is how the PMPADDRx LSB bits are handled in regard of the granularity. Their value change depending the PMPCFGx XD

31.  class StaticTranslationPlugin extends FiberPlugin with AddressTranslationService

    This plugin implement a dummy memory translation (for CPU without MMU).

    This plugin implement a dummy memory translation (for CPU without MMU). That way, the plugins like the LSU/Fetch always have a MMU-like interface, which symplify their code.