Packages

p

vexiiriscv

regfile

package regfile

Type Members

  1. case class RegFileIo(rfpp: RegFilePortParam, readsParameter: Seq[RegFileReadParameter], writesParameter: Seq[RegFileWriteParameter]) extends Bundle with Product with Serializable
  2. class RegFileMem extends Component

    Implement a register file with multiple read/write ports and different topology to imeplement those ports The bankCount is currently useless, but maybe useful in the future with execution units which can stall

  3. class RegFilePlugin extends FiberPlugin with RegfileService with InitService

    Implement a register file in the CPU and provide an API for other plugins to create read and write access ports

  4. case class RegFilePortParam(addressWidth: Int, dataWidth: Int, hartIdWidth: Int, uopIdWidth: Int) extends Product with Serializable
  5. case class RegFileRead(rfpp: RegFilePortParam, withReady: Boolean) extends Bundle with IMasterSlave with Product with Serializable
  6. case class RegFileReadParameter(withReady: Boolean) extends Product with Serializable
  7. case class RegFileWrite(rfpp: RegFilePortParam, withReady: Boolean) extends Bundle with IMasterSlave with Product with Serializable
  8. case class RegFileWriteParameter(withReady: Boolean) extends Product with Serializable
  9. case class RegFileWriter(rfSpec: RegfileSpec) extends Bundle with Product with Serializable
  10. trait RegFileWriterService extends AnyRef
  11. trait RegfileService extends AnyRef

    Provide an API which allows to create new read/write ports to a given register file.