vexiiriscv

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class ParamSimple extends AnyRef
ParamSimple is a data class which can be used to generate a collection of properly configured plugins for VexiiRiscv.
ParamSimple is a data class which can be used to generate a collection of properly configured plugins for VexiiRiscv. - you create an instance of ParamSimple - you configure it - you ask it to provide the list of VexiiRiscv plugins - you instanciate VexiiRiscv with that list of plugin - Thenthen you should get a functional VexiiRiscv.
class VexiiRiscv extends Component
This is the VexiiRiscv toplevel, it doesn't define/generate any hardware by itself, it is just a framework to register/execute plugins and bind a database to share global variables

object Generate extends App
object GenerateTilelink extends App
object Global extends AreaRoot
Define global variables for plugin to share in non-verbose ways
Define global variables for plugin to share in non-verbose ways
A few notes about physical/virtual/mixed addresses, as they are a tricky thing if you try to scrap away any unecessary bit : In RISC-V, the addresses manipulated by the CPU before the MMU can be physical or virtual. The thing is that Physical addresses are unsigned, while virtual addresses are signed (so sign extended to XLEN). So let's say you have : - 32 bits physical address width - 39 bits virtual address width Then, addresses in the CPU before the MMU (mixed addresses) need to have 40 bits (39 bits + 1 bit of sign extension), that allow for instance : - physical address trap at 0x40_0000_0000 to be stored in let's say MEPC to store that address while avoiding the sign extension
object ParamSimple
object VexiiRiscv

class ParamSimple extends AnyRef
ParamSimple is a data class which can be used to generate a collection of properly configured plugins for VexiiRiscv.
ParamSimple is a data class which can be used to generate a collection of properly configured plugins for VexiiRiscv. - you create an instance of ParamSimple - you configure it - you ask it to provide the list of VexiiRiscv plugins - you instanciate VexiiRiscv with that list of plugin - Thenthen you should get a functional VexiiRiscv.
class VexiiRiscv extends Component
This is the VexiiRiscv toplevel, it doesn't define/generate any hardware by itself, it is just a framework to register/execute plugins and bind a database to share global variables

object Generate extends App
object GenerateTilelink extends App
object Global extends AreaRoot
Define global variables for plugin to share in non-verbose ways
Define global variables for plugin to share in non-verbose ways
A few notes about physical/virtual/mixed addresses, as they are a tricky thing if you try to scrap away any unecessary bit : In RISC-V, the addresses manipulated by the CPU before the MMU can be physical or virtual. The thing is that Physical addresses are unsigned, while virtual addresses are signed (so sign extended to XLEN). So let's say you have : - 32 bits physical address width - 39 bits virtual address width Then, addresses in the CPU before the MMU (mixed addresses) need to have 40 bits (39 bits + 1 bit of sign extension), that allow for instance : - physical address trap at 0x40_0000_0000 to be stored in let's say MEPC to store that address while avoiding the sign extension
object ParamSimple
object VexiiRiscv

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