class ParamSimple extends AnyRef
ParamSimple is a data class which can be used to generate a collection of properly configured plugins for VexiiRiscv. - you create an instance of ParamSimple - you configure it - you ask it to provide the list of VexiiRiscv plugins - you instanciate VexiiRiscv with that list of plugin - Thenthen you should get a functional VexiiRiscv.
Linear Supertypes
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- ParamSimple
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Visibility
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Instance Constructors
- new ParamSimple()
Value Members
- def addOptions(parser: OptionParser[Unit]): OptionDef[Unit, Unit]
- var additionalPerformanceCounters: Int
- def alignerPluginFetchAt: Int
- var allowBypassFrom: Int
- var bootMemClear: Boolean
- var btbDualPortRam: Boolean
- var btbHashWidth: Int
- var btbSets: Int
- val debugParam: Boolean
- var decoderAt: Int
- var decoders: Int
- var dispatcherAt: Int
- var divArea: Boolean
- var divImpl: String
- var divRadix: Int
- var embeddedJtagCd: ClockDomain
- var embeddedJtagInstruction: Boolean
- var embeddedJtagNoTapCd: ClockDomain
- var embeddedJtagTap: Boolean
- var fetchForkAt: Int
- var fetchL1Enable: Boolean
- var fetchL1PmpParam: PmpPortParameter
- var fetchL1Prefetch: String
- var fetchL1ReducedBank: Boolean
- var fetchL1RefillCount: Int
- var fetchL1Sets: Int
- var fetchL1Ways: Int
- def fetchMemDataWidth: Int
- var fetchMemDataWidthMin: Int
- var fetchNoL1PmpParam: PmpPortParameter
- var fetchTpp: MmuPortParameter
- var fetchTsp: MmuStorageParameter
- var fpuFmaFullAccuracy: Boolean
- var fpuIgnoreSubnormal: Boolean
- def getName(): String
- var hartCount: Int
-
def
hashCode(): Int
- Definition Classes
- ParamSimple → AnyRef → Any
- var lanes: Int
- var lsuForkAt: Int
- var lsuHardwarePrefetch: String
- var lsuL1Coherency: Boolean
- var lsuL1Enable: Boolean
- var lsuL1PmpParam: PmpPortParameter
- var lsuL1RefillCount: Int
- var lsuL1Sets: Int
- var lsuL1Ways: Int
- var lsuL1WritebackCount: Int
- def lsuMemDataWidth: Int
- var lsuMemDataWidthMin: Int
- var lsuNoL1PmpParam: PmpPortParameter
- var lsuPmaAt: Int
- var lsuSoftwarePrefetch: Boolean
- var lsuStoreBufferOps: Int
- var lsuStoreBufferSlots: Int
- var lsuTpp: MmuPortParameter
- var lsuTsp: MmuStorageParameter
- def memDataWidth: Int
- var mulKeepSrc: Boolean
- var physicalWidth: Int
- def plugins(hartId: Int = 0): ArrayBuffer[Hostable]
- def pluginsArea(hartId: Int = 0): Area { ... /* 9 definitions in type refinement */ }
- var pmpParam: PmpParam
- var privParam: PrivilegedParam
- var regFileDualPortRam: Boolean
- var regFileSync: Boolean
- var relaxedBranch: Boolean
- var relaxedBtb: Boolean
- var relaxedDiv: Boolean
- var relaxedMulInputs: Boolean
- var relaxedShift: Boolean
- var relaxedSrc: Boolean
- var resetVector: Long
- var skipFma: Boolean
- var storeRs2Late: Boolean
- var withAlignerBuffer: Boolean
- def withBranchPredicton(): Unit
- var withBtb: Boolean
- def withCaches(): Unit
- var withCfu: Boolean
- var withDispatcherBuffer: Boolean
- var withDiv: Boolean
- var withGShare: Boolean
- var withHartIdInput: Boolean
- var withIterativeShift: Boolean
- var withLateAlu: Boolean
- def withLinux(): Unit
- var withLsuBypass: Boolean
- var withMmu: Boolean
- def withMmuSyncRead(): Unit
- var withMul: Boolean
- var withPerformanceCounters: Boolean
- var withRas: Boolean
- var withRvZb: Boolean
- var withRva: Boolean
- var withRvc: Boolean
- var withRvd: Boolean
- var withRvf: Boolean
- def withRvm(): Unit
- var withWhiteboxerOutputs: Boolean
- var xlen: Int