Type Members

1.  case class CachelessBus(p: CachelessBusParam) extends Bundle with IMasterSlave with Product with Serializable

   The fetch CachelessBus has the following caracteristics : - address in byte, always aligned on the full data width - supports out of order responses via the id signals - Only one transaction per id can be inflight at a given time

2.  case class CachelessBusParam(addressWidth: Int, dataWidth: Int, idCount: Int, cmdPersistence: Boolean) extends Product with Serializable
3.  class CachelessBusToTilelink extends Area
4.  case class CachelessCmd(p: CachelessBusParam) extends Bundle with Product with Serializable
5.  case class CachelessRsp(p: CachelessBusParam, withId: Boolean = true) extends Bundle with Product with Serializable
6.  class FetchCachelessPlugin extends FiberPlugin

   Implement the instruction fetch bus without L1 cache.

   Implement the instruction fetch bus without L1 cache. The main particularity of this implementation is that it support out of order memory busses

7.  class FetchCachelessTileLinkPlugin extends FiberPlugin
8.  case class FetchL1Bus(p: FetchL1BusParam) extends Bundle with IMasterSlave with Product with Serializable

   Here are the carracteristics of this memory bus : - Address are 'in byte, and always aligned to the cache line size - Each cmd transaction generates a burst of rsp of the cache line size - Memory responses can be out of order via the id signal - Only one transaction per id can be inflight at a given time

   Here are the carracteristics of this memory bus : - Address are 'in byte, and always aligned to the cache line size - Each cmd transaction generates a burst of rsp of the cache line size - Memory responses can be out of order via the id signal - Only one transaction per id can be inflight at a given time

   This class provide a fiew functions to bridge to other memory buses.

9.  case class FetchL1BusParam(physicalWidth: Int, dataWidth: Int, lineSize: Int, refillCount: Int, withBackPresure: Boolean) extends Product with Serializable
10.  case class FetchL1Cmd(physicalWidth: Int, refillCount: Int) extends Bundle with Product with Serializable
11.  case class FetchL1InvalidationBus() extends Bundle with Product with Serializable
12.  case class FetchL1InvalidationCmd() extends Bundle with Product with Serializable
13.  class FetchL1Plugin extends FiberPlugin with FetchL1Service with InitService

    Implement and bind a instruction L1 cache to the CPU The main particularity of this implementation is that the cache is non-blocking and canc onnect to prefetching plugins

14.  case class FetchL1Rsp(dataWidth: Int, refillCount: Int) extends Bundle with Product with Serializable
15.  trait FetchL1Service extends AnyRef
16.  class FetchL1TileLinkPlugin extends FiberPlugin
17.  class FetchPipelinePlugin extends FiberPlugin with PipelineService

    Provide a fethc pipeline skeleton, used by other plugins to compose the fethc pipeline.

18.  case class FetchProbe() extends Bundle with Product with Serializable
19.  trait InitService extends AnyRef

    After the CPU reset, this service allows a plugin to make the CPU wait longer before starting fetching instruction.

20.  case class JumpCmd(laneAgeWidth: Int) extends Bundle with Product with Serializable

    Interface which ask the CPU to start fetching another PC.

21.  class PcPlugin extends FiberPlugin with PcService
22.  trait PcService extends AnyRef

    Service which mainly allows other plugins to manipulate the PC being fetched

23.  case class PcServiceHoldPortSpec(hartId: Int, valid: Bool) extends Product with Serializable
24.  case class PrefetchCmd() extends Bundle with Product with Serializable
25.  class PrefetcherNextLinePlugin extends PrefetcherPlugin
26.  abstract class PrefetcherPlugin extends FiberPlugin