Type Members

1.  class AgedArbiter[T <: Data] extends Area
2.  case class AgedArbiterUp[T <: Data](valid: Bool, payload: T, age: Int, laneAge: UInt, subAge: Int) extends Product with Serializable
3.  trait CauseUser extends AnyRef
4.  trait CommitService extends AnyRef
5.  case class Delegator(enable: Bool, privilege: Int) extends Product with Serializable
6.  case class DivCmd(width: Int, radixBits: Int) extends Bundle with Product with Serializable
7.  class DivComp extends Component
8.  case class DivIo(width: Int, radixBits: Int) extends Bundle with Product with Serializable
9.  class DivRadix extends DivComp

   Implement a unsigned hardware divided which supports radix 2 and 4 (1 and 2 bits per cycle being solved) Radix 4 is supported by "brutfocfing" all 4 values the next 2 bits of the division could be, and selecting the bigggest fit.

10.  class DivRadix2 extends DivComp
11.  case class DivRsp(width: Int) extends Bundle with Product with Serializable
12.  class EmbeddedRiscvJtag extends FiberPlugin

    This is an optional plugin which will integrate the whole RISC-V debug infrastructure in the CPU itself instead of letting that to the SoC toplevel.

    This is an optional plugin which will integrate the whole RISC-V debug infrastructure in the CPU itself instead of letting that to the SoC toplevel. So it integrate the jtag TAP (DMI) and the RISC-V debug "hub" (DM). This ease the integration of VexiiRiscv into simple SoC.

13.  case class ExceptionSpec(id: Int, delegators: List[Delegator]) extends Product with Serializable
14.  trait InflightService extends AnyRef
15.  case class InterruptSpec(cond: Bool, id: Int, privilege: Int, delegators: List[Delegator]) extends Product with Serializable
16.  class LsuTriggerBus extends Bundle
17.  trait LsuTriggerService extends AnyRef
18.  class PerformanceCounterPlugin extends FiberPlugin with PerformanceCounterService

    This plugin implement the performance counters in a very tricky way to save area.

    This plugin implement the performance counters in a very tricky way to save area. The RISC-V spec specified 64 bits per counter, and that is kinda expensive to implement FPGA. So in this implementation, Only 8 bits registers are used for each counters, which are flushed into their 64 bits CSR ram when their MSB is set

    To figure out the actual performance events implement in VexiiRIscv, look at vexiiriscv.misc.PerformanceCounterService

19.  trait PerformanceCounterService extends AnyRef

    This service allows other plugins to generate new event sources for the PMU

20.  class PipelineBuilderPlugin extends FiberPlugin

    The funciton of this plugin is to collect all the pipeline parts defined by the other's PipelineService plugins.

    The funciton of this plugin is to collect all the pipeline parts defined by the other's PipelineService plugins. and then invoke the spinal.lib.misc.pipeline.builder on them in order to finalize the pipelines hardware.

21.  trait PipelineService extends AnyRef
22.  case class PrivilegedParam(withSupervisor: Boolean, withUser: Boolean, withUserTrap: Boolean, withRdTime: Boolean, withDebug: Boolean, mstatusFsInit: Int, debugTriggers: Int, debugTriggersLsu: Boolean, vendorId: Int, archId: Int, impId: Int) extends Product with Serializable
23.  class PrivilegedPlugin extends FiberPlugin with CommitService with LsuTriggerService

    This implements the large majority of the RISC-V privileged spec : - Most CSR - Interrupts - Debug interface (RISC-V debug spec)

24.  class Reservation extends AnyRef
25.  case class Trap(laneAgeWidth: Int, full: Boolean) extends Bundle with Product with Serializable
26.  case class TrapPending() extends Bundle with Product with Serializable
27.  class TrapPlugin extends FiberPlugin with TrapService

    Mainly, this plugin implement a state-machine which handle regular traps (interrupt/exception), but also a set of special "hardware" trap used by the CPU to handle special cases as instruction retry/fences, MMU refill, ...

    Mainly, this plugin implement a state-machine which handle regular traps (interrupt/exception), but also a set of special "hardware" trap used by the CPU to handle special cases as instruction retry/fences, MMU refill, ...

    Also, as VexiiRiscv implements a few large CSR directly into a sharder memory (mepc, mtvec, ...), the TrapPlugin state-machine handles the hardware read/write with those CSR (durring trap, mret, ...).

28.  trait TrapService extends Area

    fetch (page fault, access fault) decode (illegal) execute - miss aligned load/store/branch - page fault, access fault - ecall, ebreak

    fetch (page fault, access fault) decode (illegal) execute - miss aligned load/store/branch - page fault, access fault - ecall, ebreak

    To do a trap request : - Flush all youngers instructions - Store cause / tval - Rise trap flag in the pipe (this will disable side-effects)

29.  case class TrapSpec(bus: Flow[Trap], age: Int, subAge: Int) extends Product with Serializable