tester

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class FsmGetc extends FsmTask
trait FsmHal extends AnyRef
Here are a set of classes which are used to build directed VexiiRiscv test cases.
Here are a set of classes which are used to build directed VexiiRiscv test cases. For instance, to test if VexiiRiscv can boot linux in a simulation, they can be used to encode the expected sequence of terminal stdout/stdin to observe/produce until the sim can be considered a success.
class FsmPutc extends FsmTask
class FsmSleep extends FsmTask
class FsmSuccess extends FsmTask
trait FsmTask extends AnyRef
class TestArgs extends AnyRef
This is a test argument builder, which is just there to make it easy to build specific testbenches in the regression environnement
class TestBenchServerConnection extends Thread
class TestOptions extends AnyRef
This class store a bunch of options about how to run a VexiiRiscv testbench, including which binaries need to be loaded in memory.
This class store a bunch of options about how to run a VexiiRiscv testbench, including which binaries need to be loaded in memory.
It also include a "test" function actualy contains the simulation code itself, and when invoked will run the whole simulation.
class TlTbParam extends AnyRef
class TlTbTop extends Component

object TestBench extends App
This is the main VexiiRiscv testbench, you can invoke it from command line and is based on the TestOptions class
object TestBenchServer extends App
So, this is a quite special scala App.
So, this is a quite special scala App. It allows to start a VexiiRiscv simulation server for a specific configuration.
here is an example how you can start the server and spawn a simulation on it : sbt "runMain vexiiriscv.tester.TestBenchServer --with-rvm" Then wait for : [info] [Progress] Verilator compilation started [info] [Progress] Verilator compilation done in 2591.432 ms [info] Waiting for connections Then, in another terminal, you can spawn a new simulation via for instance : echo '--load-elf ext/NaxSoftware/baremetal/dhrystone/build/rv32ima/dhrystone.elf' | nc localhost 8189
The advantage of this aproache over runnint the sbt "runMain vexiiriscv.tester.TestBench" is that you can "warm up" a simulator, meaning running the generation and compilation of the hardware, and then invoke the simulations many time on it with close to zero startup time. This was done to run the many embench benchmarks efficiently.
object TlTbSim extends App

class FsmGetc extends FsmTask
trait FsmHal extends AnyRef
Here are a set of classes which are used to build directed VexiiRiscv test cases.
Here are a set of classes which are used to build directed VexiiRiscv test cases. For instance, to test if VexiiRiscv can boot linux in a simulation, they can be used to encode the expected sequence of terminal stdout/stdin to observe/produce until the sim can be considered a success.
class FsmPutc extends FsmTask
class FsmSleep extends FsmTask
class FsmSuccess extends FsmTask
trait FsmTask extends AnyRef
class TestArgs extends AnyRef
This is a test argument builder, which is just there to make it easy to build specific testbenches in the regression environnement
class TestBenchServerConnection extends Thread
class TestOptions extends AnyRef
This class store a bunch of options about how to run a VexiiRiscv testbench, including which binaries need to be loaded in memory.
This class store a bunch of options about how to run a VexiiRiscv testbench, including which binaries need to be loaded in memory.
It also include a "test" function actualy contains the simulation code itself, and when invoked will run the whole simulation.
class TlTbParam extends AnyRef
class TlTbTop extends Component

object TestBench extends App
This is the main VexiiRiscv testbench, you can invoke it from command line and is based on the TestOptions class
object TestBenchServer extends App
So, this is a quite special scala App.
So, this is a quite special scala App. It allows to start a VexiiRiscv simulation server for a specific configuration.
here is an example how you can start the server and spawn a simulation on it : sbt "runMain vexiiriscv.tester.TestBenchServer --with-rvm" Then wait for : [info] [Progress] Verilator compilation started [info] [Progress] Verilator compilation done in 2591.432 ms [info] Waiting for connections Then, in another terminal, you can spawn a new simulation via for instance : echo '--load-elf ext/NaxSoftware/baremetal/dhrystone/build/rv32ima/dhrystone.elf' | nc localhost 8189
The advantage of this aproache over runnint the sbt "runMain vexiiriscv.tester.TestBench" is that you can "warm up" a simulator, meaning running the generation and compilation of the hardware, and then invoke the simulations many time on it with close to zero startup time. This was done to run the many embench benchmarks efficiently.
object TlTbSim extends App

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