Type Members

1.  class BarrelShifterPlugin extends ExecutionUnitElementSimple

   Implements the RISC-V integer shift instructions use a single left barrel shifter pre/post bit reverse for right shifts

2.  class BranchPlugin extends ExecutionUnitElementSimple with LearnSource

   Implement the branch/jump handeling in the execute stage.

   Implement the branch/jump handeling in the execute stage. Depending if the CPU has a BTB it work completly differently. - If there is no BTB, then the plugin work very "normaly" and just execute the incoming instructions - If there is a BTB, then the goal of the plugin is to check if the predictions done were right, and correct if necessary

   In the case there is multiple BranchPlugin on a given execution lane, they will share quite a bit of hardware via the PcCalc Area. Also, only the last instance of BranchPlugin on a given execution lane will feed the LearnPlugin via its LearnSource service. This reduce the hardware area aswell as reducing the possibility of multiple BranchPlugin providing LearnSource request at the same time.

3.  case class CompletionPayload() extends Bundle with Product with Serializable
4.  trait CompletionService extends AnyRef

   Allows a plugin to publish a list of interface which provide micro-op completion notifications

5.  class CsrAccessPlugin extends FiberPlugin with CsrService

   Implements the RISC-V CSR read/write instructions, aswell as provide an API for other plugin to populate the CSR space.

   Implements the RISC-V CSR read/write instructions, aswell as provide an API for other plugin to populate the CSR space. In other words, this plugin do not define any CSR, but provide an API to define them (that API is defined in CsrService).

   To help with the FMax, CSR accesses are implemented by using a state-machine. Accesses are done over 4 cycles : idle -> read -> write -> completion

   This maybe a bit overkilled, but as the CSR access isn't critical for the IPC, better to much cycles than not enough.

6.  case class CsrBus() extends Bundle with Product with Serializable
7.  case class CsrDecode() extends Bundle with Product with Serializable
8.  class CsrHartApi extends AnyRef
9.  case class CsrIsReadingCsr(csrFilter: Any, value: Bool) extends CsrSpec with Product with Serializable
10.  case class CsrIsReadingHartId(hartId: Int, value: Bool) extends Product with Serializable
11.  case class CsrListFilter(mapping: Seq[Int]) extends Nameable with Product with Serializable
12.  case class CsrOnDecode(csrFilter: Any, priority: Int, body: () ⇒ Unit) extends CsrSpec with Product with Serializable
13.  case class CsrOnRead(csrFilter: Any, onlyOnFire: Boolean, body: () ⇒ Unit) extends CsrSpec with Product with Serializable
14.  case class CsrOnReadData(bitOffset: Int, value: Bits) extends Product with Serializable
15.  case class CsrOnReadToWrite(csrFilter: Any, body: () ⇒ Unit) extends CsrSpec with Product with Serializable
16.  case class CsrOnWrite(csrFilter: Any, onlyOnFire: Boolean, body: () ⇒ Unit) extends CsrSpec with Product with Serializable
17.  class CsrRamAllocation extends AnyRef
18.  class CsrRamPlugin extends FiberPlugin with CsrRamService with InitService

    Implement a RAM and provide an API (CsrRamService) that allows other plugins to : - Staticaly allocate memory space - Map the allocated memory space on the CPU CSR instruction - Create new read/write access ports to the memory.

    Implement a RAM and provide an API (CsrRamService) that allows other plugins to : - Staticaly allocate memory space - Map the allocated memory space on the CPU CSR instruction - Create new read/write access ports to the memory.

    This plugin is used mostly to implement large CSR as mepc, mtval, aswell as for implementing the performance counters

19.  case class CsrRamRead(addressWidth: Int, dataWidth: Int, priority: Int) extends Bundle with Product with Serializable
20.  trait CsrRamService extends Area
21.  case class CsrRamWrite(addressWidth: Int, dataWidth: Int, priority: Int) extends Bundle with Product with Serializable
22.  case class CsrRead() extends Bundle with Product with Serializable
23.  trait CsrService extends AnyRef

    Service which provide a bunch of primitives allowing to map some hardware to the CSR address space

24.  class CsrSpec extends AnyRef
25.  case class CsrWrite() extends Bundle with Product with Serializable
26.  case class CsrWriteCancel(csrFilter: Any, cond: Bool) extends CsrSpec with Product with Serializable
27.  class DivPlugin extends ExecutionUnitElementSimple with DivReuse

    Implement the RISC-V division instruction using an unsigned divider.

    Implement the RISC-V division instruction using an unsigned divider. but the actual division hardware is provided through a landa function parameter.

28.  trait DivReuse extends AnyRef
29.  class EnvPlugin extends ExecutionUnitElementSimple

    Implements a bunch of special instruction which always traps into the TrapPlugin.

    Implements a bunch of special instruction which always traps into the TrapPlugin. (ecall, ebreak, mret, fences, efi, ...)

30.  class ExecuteLanePlugin extends FiberPlugin with ExecuteLaneService with CompletionService with InflightService

    Implements an execution lane : - Read the register files - Implement register files bypass logic - Register which execution layer are working on that lane - ...

31.  trait ExecuteLaneService extends Area

    Provide an API to access an exeuction lanes.

32.  class ExecutePipelinePlugin extends FiberPlugin with PipelineService

    Provide the execution pipeline skeleton for the ExecuteLanePlugin

    Provide the execution pipeline skeleton for the ExecuteLanePlugin

    The flow control of the whole execute pipeline is interlocked / do not collapse bubbles (freezeIt/isFreezed) The reason is to preserve the relative timings between the instruction as the dispatcher requires it.

33.  abstract class ExecutionUnitElementSimple extends FiberPlugin

    This is a simple skeleton to ease the implementation of simple execution plugins.

    This is a simple skeleton to ease the implementation of simple execution plugins. It assume a single writeback and a single completion For a simple example, look at the IntAluPlugin.

34.  class IntAluPlugin extends ExecutionUnitElementSimple

    Implements most of the integer processing instructions (but not the shift/mul/div)

35.  class IntFormatPlugin extends FiberPlugin

    This plugin provide an API which allows other plugins to generate an hardware interface to writeback integer results back to the register file with some specified hardware formating : - sign extension - zero extension

    This plugin provide an API which allows other plugins to generate an hardware interface to writeback integer results back to the register file with some specified hardware formating : - sign extension - zero extension

    One nice thing is that the hardware which does the formating is shared between all the instructions which opperate in the same stage.

36.  class IterativeShifterPlugin extends ExecutionUnitElementSimple

    Iterative Shifter

    Iterative Shifter

    The default parameters are optimized for 6-input LUT devices (since it will use 4:1 muxes (load/shift 1/shift 8/flip), but additional shifts can be added to increase performance. Only 2**n shift distances are well supported, other distances will lead to suboptimal shift sequence if needed multiple times.

    lateResult can be used to make the done logic slighly smaller, which should not be needed for the default configuration. Enabling it costs 1 cycle for all shifts.

37.  class LaneLayer extends AnyRef

    Used to model an execution lane layer.

    Used to model an execution lane layer. For isntance if you have a dual issue pipeline with early and late ALUs, then you will have 4 LaneLayers

    So, this class will store the model of every micro-op that it supports, aswell as the timing that they have (when do they use RS1/RS2, when do they provide a RD value, ..., by using the UopLayerSpec class.

38.  case class LsuL1Bus(p: LsuL1BusParameter) extends Bundle with IMasterSlave with Product with Serializable

    Define the VexiiRiscv LsuL1 native memory bus.

    Define the VexiiRiscv LsuL1 native memory bus. Its memory coherency protocol is close to tilelink, but has a few minor twists : - probe request may fail in Vexii, and so, need to be retried - probe request which produce a permition downgrade will be acknoledged on the probe.rsp bus, but will also generate a write.cmd writeback (which can be data-less)

    All memory transaction are assumed to be the size of a cache line, including probes.

39.  case class LsuL1BusParameter(addressWidth: Int, dataWidth: Int, readIdCount: Int, writeIdCount: Int, probeIdWidth: Int, ackIdWidth: Int, lineSize: Int, withReducedBandwidth: Boolean, withCoherency: Boolean) extends Product with Serializable
40.  case class LsuL1ProbeBus(p: LsuL1BusParameter) extends Bundle with IMasterSlave with Product with Serializable
41.  case class LsuL1ProbeCmd(p: LsuL1BusParameter) extends Bundle with Product with Serializable
42.  case class LsuL1ProbeRsp(p: LsuL1BusParameter, fromProbe: Boolean) extends Bundle with Product with Serializable
43.  case class LsuL1ReadAck(p: LsuL1BusParameter) extends Bundle with Product with Serializable
44.  case class LsuL1ReadBus(p: LsuL1BusParameter) extends Bundle with IMasterSlave with Product with Serializable
45.  case class LsuL1ReadCmd(p: LsuL1BusParameter) extends Bundle with Product with Serializable
46.  case class LsuL1ReadRsp(p: LsuL1BusParameter) extends Bundle with Product with Serializable
47.  case class LsuL1WriteBus(p: LsuL1BusParameter) extends Bundle with IMasterSlave with Product with Serializable
48.  case class LsuL1WriteCmd(p: LsuL1BusParameter) extends Bundle with Product with Serializable
49.  case class LsuL1WriteRsp(p: LsuL1BusParameter) extends Bundle with Product with Serializable
50.  class MulPlugin extends ExecutionUnitElementSimple with MulReuse

    Implement RISC-V multiplication instructions by subdividing them into partial ones.

    Implement RISC-V multiplication instructions by subdividing them into partial ones. For instance, 32bits x 32 bits = a[15: 0]*b[15: 0] + a[15: 0]*b[31:16] + a[31:16]*b[15: 0] + a[31:16]*b[31:16]

    This calculation is splited over multiple stages to get a good FMax on FPGA (in general)

    bufferedHigh can be used to buffer the mulh instruction one extra cycle on the stage to improve the FMax at the cost of one idle cycle.

51.  trait MulReuse extends AnyRef
52.  class OpKeys extends SrcKeys
53.  class PcCalc extends Area
54.  case class RdSpec(rf: RegfileSpec, DATA: Payload[Bits], broadcastedFrom: Int, rfReadableFrom: Int) extends Product with Serializable

    Used to model the RISC-V RD usage of a given micro-op

55.  case class RsSpec(rf: RegfileSpec, rs: RfRead) extends Product with Serializable

    Used to model the RISC-V RS1/RS2 usage of a given micro-op

56.  class RsUnsignedPlugin extends FiberPlugin

    This plugin takes the integer RS1/RS2 and unsigne them.

    This plugin takes the integer RS1/RS2 and unsigne them. This can be used by other plugins to share that hardware. ex : unsigned divider, unsigned multiplier, ...

57.  class SimdAddPlugin extends ExecutionUnitElementSimple
58.  class SimdAddRawPlugin extends FiberPlugin

    Same as SimdAddPlugin, but wihtout the help of the ExecutionUnitElementSimple skeleton.

59.  class Src1Keys extends SrcKeys
60.  class Src2Keys extends SrcKeys
61.  class SrcKeys extends AnyRef
62.  class SrcPlugin extends FiberPlugin

    This plugin takes the RS1/RS2/Instruction values early in the execute pipeline and produce SRC1/SRC2/ADD_SUB/LESS values out of it.

    This plugin takes the RS1/RS2/Instruction values early in the execute pipeline and produce SRC1/SRC2/ADD_SUB/LESS values out of it.

    Other plugins can specify what processing they are interrested for SRC1/SRC2 in function of which instruction is being executed. SRC1/SRC2 are muxed values between RS1/RS2 and literals in the instruction. ADD_SUB can be either the addition or substraction between SRC1 and SRC2 LESS specifies if SRC1 is less than SRC2 (unsigned or signed comparison)

63.  case class UopImplKey(uop: MicroOp, name: LaneLayer) extends Product with Serializable
64.  class UopLayerSpec extends AnyRef

    Specfies how a given MicroOp is implemented in a given LaneLayer - RD/RS1/RS2 timings and usages - Completion timing - Flush supported/behaviour - Additional decoding required - Shared hardware reservations

65.  class WriteBackPlugin extends FiberPlugin with RegFileWriterService

    This plugin allows other plugins to create interface to write in the register file from where they want in the pipeline.

    This plugin allows other plugins to create interface to write in the register file from where they want in the pipeline. The trick is that this plugin will only instanciate one register file write port at the last stage, and pipeline all the write interface created for the other plugins to that point.

66.  class ZbaPlugin extends ExecutionUnitElementSimple
67.  class ZbbByteReversePlugin extends ExecutionUnitElementSimple
68.  class ZbbCountPlugin extends ExecutionUnitElementSimple
69.  class ZbbExtendPlugin extends ExecutionUnitElementSimple
70.  class ZbbLogicPlugin extends ExecutionUnitElementSimple
71.  class ZbbMinMaxPlugin extends ExecutionUnitElementSimple
72.  class ZbbOrPlugin extends ExecutionUnitElementSimple
73.  class ZbbRotatePlugin extends ExecutionUnitElementSimple
74.  class ZbcPlugin extends ExecutionUnitElementSimple
75.  class ZbsPlugin extends ExecutionUnitElementSimple