Type Members

1.  case class FloatUnpacked(p: FloatUnpackedParam) extends Bundle with Product with Serializable

   This is the floating format used in the FPU ALUs Unlike ieee 754, it doesn't support subnormals, so, to convert from ieee 754 to FloatUnpacked accurately on subnormals, the FloatUnpacked need to have an extended exponent field, allowing to cover the subnormal numbers as if they were normal.

2.  case class FloatUnpackedParam(exponentMax: Int, exponentMin: Int, mantissaWidth: Int) extends Product with Serializable
3.  class FpuAdd extends Area

   This Area can be used to implement and bind a floating point adder on a given pipeline.

4.  class FpuAddPlugin extends FiberPlugin

   Add the floating point add instruction the CPU.

   Add the floating point add instruction the CPU. Rely on the FpuAddSharedPlugin to do the maths.

5.  case class FpuAddSharedCmd(p1: FloatUnpackedParam, p2: FloatUnpackedParam, ats: Seq[Int]) extends Bundle with Product with Serializable
6.  class FpuAddSharedPlugin extends FiberPlugin

   This plugin implements an shared hardware floating point adder and provide an API for other plugins to time share it.

   This plugin implements an shared hardware floating point adder and provide an API for other plugins to time share it. In practice, the RISC-V fadd and fma instruction use it. The actual adder hadware is provided by the FpuAdd plugin.

7.  class FpuAddSharedPort extends Area
8.  class FpuClassPlugin extends FiberPlugin

   Provide the RISC-V fclass instruction, which allows to figure out the kind of a given floating point number (normal, submornal, infinit, nan, ...)

9.  class FpuCmpPlugin extends FiberPlugin

   Implement a bunch of simple RISC-V floating point instruction : - sign manipulation - min/max - compare

10.  class FpuCsrPlugin extends FiberPlugin with FpuDirtyService

    Provide the RISC-V FPU csr (rounding mode and flags)

11.  trait FpuDirtyService extends AnyRef
12.  class FpuDivPlugin extends FiberPlugin

    Implement the RISC-V floating point division.

    Implement the RISC-V floating point division. The mantissa division is implemented by reusing the hardware from the integer divider Not having to deal with subnormal numbers helps, as it fix the range of the mantissa between [1.0, 2.0[

13.  class FpuF2iPlugin extends FiberPlugin

    Implement the RISC-V floating point to integer convertions

14.  case class FpuFlags() extends Bundle with Product with Serializable
15.  class FpuFlagsWritebackPlugin extends FiberPlugin

    Handle the update of the FPU flags for all inflight instruction (commited and uncommited)

16.  case class FpuFlagsWritebackPort(atsSpec: Seq[Int]) extends Bundle with Product with Serializable
17.  class FpuMulPlugin extends FiberPlugin

    Add the floating point mul instruction the CPU.

    Add the floating point mul instruction the CPU. The mantissa multiplier is implemented by reusing the hardware from the integer multiplier

18.  class FpuMvPlugin extends FiberPlugin

    Implement the RISC-V floating point <> integer binary casts

19.  case class FpuPackerCmd(p: FloatUnpackedParam, ats: Seq[Int]) extends Bundle with Product with Serializable
20.  class FpuPackerPlugin extends FiberPlugin with RegFileWriterService

    Implement the floating point rounding, recode the result into (ieee 754) and then writeback it back into the register file using the WriteBackPlugin.

    Implement the floating point rounding, recode the result into (ieee 754) and then writeback it back into the register file using the WriteBackPlugin. Subnormal recoding will stall the pipeline 2 extra cycles to save FMax.

21.  class FpuPackerPort extends Area
22.  case class FpuSqrt(mantissaWidth: Int) extends Component with Product with Serializable

    Implement the floating point mantissa SQRT

23.  case class FpuSqrtCmd(mantissaWidth: Int) extends Bundle with Product with Serializable
24.  class FpuSqrtPlugin extends FiberPlugin

    Implement the RISC-V floating point SQRT instruction by using the FpuSqrt hardware.

    Implement the RISC-V floating point SQRT instruction by using the FpuSqrt hardware. Not having to deal with subnormal numbers helps, as it fix the range of the mantissa between [1.0, 2.0[

25.  case class FpuSqrtRsp(mantissaWidth: Int) extends Bundle with Product with Serializable
26.  class FpuUnpackerPlugin extends FiberPlugin

    Recode the floating point number comming from the register file to get rid of subnormal numbers by extending the exponant range instead.

    Recode the floating point number comming from the register file to get rid of subnormal numbers by extending the exponant range instead. Getting ride of subnormal helps various floating point operations, as it ensure that the range of the mantissa stay between [1.0, 2.0[

    When a subnormal number come in, the pipeline will be stuck for a few cycles in order to preserve the FMax.

27.  class FpuXxPlugin extends FiberPlugin

    Convert floating point 32 bits to/from 64 bits packAt at 1 to reduce timing presure (unpack -> pack)

    Convert floating point 32 bits to/from 64 bits packAt at 1 to reduce timing presure (unpack -> pack)

    The FpuPackerPlugin will do the heavy work (rounding)