Type Members

1.  class AguFrontend extends Api with Area

   The AguFrontend provide an Area which define all RISC-V memory load/store/atomic instruction/microops aswell as a set of decodings (see AguPlugin object above) It can be used by various LSU implementations as a base.

2.  trait CmoService extends AnyRef

   Allows a plugin to specifies to others that CMO are implemented This is used by the IntAluPlugin to avoid overlaping the ORI instruction with the CMO's prefetch instructions

3.  case class LockPort() extends Bundle with IMasterSlave with Product with Serializable
4.  case class LsuCachelessBus(p: LsuCachelessBusParam) extends Bundle with IMasterSlave with Product with Serializable
5.  case class LsuCachelessBusParam(addressWidth: Int, dataWidth: Int, hartIdWidth: Int, uopIdWidth: Int, withAmo: Boolean, pendingMax: Int) extends Product with Serializable
6.  trait LsuCachelessBusProvider extends AnyRef

   Implemented by the LsuPlugins to provide the MmuPlugin's hardware page walker a way to access the memory

7.  class LsuCachelessBusToTilelink extends Area

   Simple bridge to tilelink which avoid ordering issues by keeping track of all inflight memory transactions and halt new request if a conflict is detected.

8.  case class LsuCachelessCmd(p: LsuCachelessBusParam) extends Bundle with Product with Serializable

   VexiiRiscv native memory bus used for uncached and IO memory accesses.

   VexiiRiscv native memory bus used for uncached and IO memory accesses. It it meant to be easily bridged to other memory busses. Responses are out of order and can be reordered via the id field. It also supports AMO/LR/SC atomics

9.  class LsuCachelessPlugin extends FiberPlugin with DBusAccessService with LsuCachelessBusProvider

   Implements an LSU without any cache.

   Implements an LSU without any cache. The tricky thing about this implementation, is the withSpeculativeLoadFlush parameter, which allows the plugin to speculatively emit non-io memory load to the memory system, even if the load result may be trashed away.

   The plugin does support MMU aswell as atomic instruction. This allows to run linux without data cache :D. This is usefull from a verification perspective.

   To get good timings on FPGA in a SoC, consider setting : - forkAt = 1 - joinAt = 2

   This allows the memory bus CMD to have very relaxed timings by avoiding the XLEN bits adder aswell as the PMA data path. The down side is that the memory bus respons data path timings are stressed, but as this only impact the data path (no control path), it seems to be generaly better.

10.  case class LsuCachelessRsp(p: LsuCachelessBusParam, withId: Boolean = true) extends Bundle with Product with Serializable
11.  class LsuCachelessTileLinkPlugin extends FiberPlugin

    Bridge the LsuCachelessPlugin to a tilelink Node using LsuCachelessBusToTilelink

12.  case class LsuCommitProbe() extends Bundle with Product with Serializable
13.  case class LsuL1Cmd() extends Bundle with Product with Serializable
14.  case class LsuL1InvalidationBus() extends Bundle with Product with Serializable
15.  case class LsuL1InvalidationCmd() extends Bundle with Product with Serializable

    Used by the TrapPlugin to flush the L1 data cache durring a fence.i instruction

16.  class LsuL1Plugin extends FiberPlugin with InitService with LsuL1Service
17.  trait LsuL1Service extends AnyRef
18.  class LsuL1TileLinkPlugin extends FiberPlugin

    Bridge the LsuL1Plugin to a Tilelink node

19.  class LsuL1TlPlugin extends FiberPlugin
20.  class LsuPlugin extends FiberPlugin with DBusAccessService with LsuCachelessBusProvider with LsuService with CmoService

    The LsuPlugin does many things : - Handle the AGU (Address Generation Unit) - Interface with the L1 cache - Handle the MMU integration - Implement the PMA checks(Physical Memory Access) - Implement the IO accesses - Implement the AMO/LR/SC instructino - Impplement a store buffer - Implement the prefetching request - Implement RISC-V debug triggers related to memory load/store

    The LsuPlugin does many things : - Handle the AGU (Address Generation Unit) - Interface with the L1 cache - Handle the MMU integration - Implement the PMA checks(Physical Memory Access) - Implement the IO accesses - Implement the AMO/LR/SC instructino - Impplement a store buffer - Implement the prefetching request - Implement RISC-V debug triggers related to memory load/store

    So, it has a lot of different functionalities which sometimes are thigtly coupled together in order to reduce area and increase FMax which can make it challenging to read.

21.  trait LsuService extends AnyRef
22.  class LsuTileLinkPlugin extends FiberPlugin

    Bridge the LsuPlugin io bus to tilelink node

23.  case class PrefetchCmd() extends Bundle with Product with Serializable
24.  class PrefetcherNextLinePlugin extends PrefetcherPlugin
25.  abstract class PrefetcherPlugin extends FiberPlugin
26.  class PrefetcherRptPlugin extends PrefetcherPlugin with InitService

    Implements load/store predictor for the LSU.

    Implements load/store predictor for the LSU. See https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/Memory/index.html#prefetchrptplugin for more details

27.  case class StoreBufferOp() extends Bundle with Product with Serializable