Packages

package test

Type Members

  1. abstract class PeripheralEmulator extends AnyRef

    This is used for simulations, it can be used to emulate a minmal sets of peripherals : - Terminal binded to stdin stdout - RISC-V CLINT - Simulation pass/fail commands

  2. class VexiiRiscvProbe extends AnyRef

    VexiiRiscvProbe can be used in a simulation to probe the activities of VexiiRiscv and notifies a list of TraceBackend with what happened (ex commit, memory load, memory store, trap, ...)

    VexiiRiscvProbe can be used in a simulation to probe the activities of VexiiRiscv and notifies a list of TraceBackend with what happened (ex commit, memory load, memory store, trap, ...)

    There is a few usefull backends : - RVLS to check that the simulated VexiiRiscv CPU is doing things right - A file backend, to keep a text file trace of what happened (instead of having to look into a waveform)

    It also keep a trace of various performance metrics, as the IPC, branch miss rate, ...

  3. class WhiteboxerPlugin extends FiberPlugin

    This plugin is here to ease and "standardise" the way a simulation can look at a VexiiRiscv core and figure out what it is doing.

    This plugin is here to ease and "standardise" the way a simulation can look at a VexiiRiscv core and figure out what it is doing. It also generate a large set of easy to read signals that can be read in a waveform.

    All the "Proxy" are there to reduce the overhead of reading hardware signals in a SpinalHDL simulation.