Packages

c

vexiiriscv.soc.litex

LitexMemoryRegion

case class LitexMemoryRegion(mapping: SizeMapping, mode: String, bus: String) extends Product with Serializable

Because VexiiRiscv implement PMA (Physical Memory Access) checking staticaly, we need to know what is mapped behind the litex memory busses.

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Serializable, Serializable, Product, Equals, AnyRef, Any
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  1. LitexMemoryRegion
  2. Serializable
  3. Serializable
  4. Product
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Instance Constructors

  1. new LitexMemoryRegion(mapping: SizeMapping, mode: String, bus: String)

Value Members

  1. val bus: String
  2. def isCachable: Boolean
  3. def isExecutable: Boolean
  4. val mapping: SizeMapping
  5. val mode: String
  6. def onMemory: Boolean
  7. def onPeripheral: Boolean