Type Members

1.  case class LitexMemoryRegion(mapping: SizeMapping, mode: String, bus: String) extends Product with Serializable

   Because VexiiRiscv implement PMA (Physical Memory Access) checking staticaly, we need to know what is mapped behind the litex memory busses.

2.  class Soc extends Component

   This is the VexiiRiscv SoC toplevel used with Litex.

   This is the VexiiRiscv SoC toplevel used with Litex. - Based on tilelink for its memory interconnect - Integrate the PLIC and CLINT peripherals - Access the main memory through a dedicated AXI bus instead of the regular litex wishbone (for performance reasons) - Can be multicore - Implement memory coherency between the code and a AXI DMA access bus - Has an option L2 cache - Supports JTAG debug - Supports a SpinalHDL HDMI and Ethernet controller

   The SpinalHDL RGMII ethernet linux driver is implemented here : - https://github.com/Dolu1990/litex-linux/tree/spinal-sgmac/drivers/net/ethernet/spinal

   It can be enabled in linux DTS via for instance : mac0: mac@f1000000 { compatible = "spinal,sgeth"; reg = <0xf1000000 0x100>, <0xf1000100 0x100>, <0xf1000200 0x100>; reg-names = "mac", "tx-dma", "rx-dma"; interrupts = <40 41>; interrupt-names = "tx-dma", "rx-dma"; status = "okay"; };

   Also, be sure the the PLIC's riscv,ndev is set high enough (ex riscv,ndev = <64>; )

3.  class SocConfig extends AnyRef

   Litex SoC configuration object.