class Logic extends Area
Linear Supertypes
Ordering
- Alphabetic
- By Inheritance
Inherited
- Logic
- Area
- OverridedEqualsHashCode
- ValCallbackRec
- ValCallback
- NameableByComponent
- Nameable
- ContextUser
- ScalaLocated
- GlobalDataUser
- OwnableRef
- AnyRef
- Any
- Hide All
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Visibility
- Public
- All
Instance Constructors
- new Logic()
Type Members
- class CompletionProxy extends AnyRef
- class CsrProxy extends AnyRef
- class DecodeProxy extends AnyRef
- class DispatchProxy extends AnyRef
- class ExecuteProxy extends AnyRef
- class FetchProxy extends AnyRef
- class FlushProxy extends AnyRef
- class LearnProxy extends AnyRef
- class LoadExecuteProxy extends AnyRef
- class PerfProxy extends AnyRef
- abstract class Proxies extends AnyRef
-
abstract
type
RefOwnerType
- Definition Classes
- OwnableRef
- class RfWriteProxy extends AnyRef
- class SerializedProxy extends AnyRef
- class StoreBroadcastProxy extends AnyRef
- class StoreCommitProxy extends AnyRef
- class StoreConditionalProxy extends AnyRef
- class TrapProxy extends AnyRef
Value Members
-
val
_context: Capture
- Definition Classes
- Area
- val buildBefore: RetainerGroup
-
def
childNamePriority: Byte
- Definition Classes
- Area
- val commits: Area { ... /* 7 definitions in type refinement */ }
- val completions: Area { val ports: Seq[spinal.lib.Flow[vexiiriscv.execute.CompletionPayload]] }
-
def
component: Component
- Definition Classes
- ContextUser
- val csr: Option[Area { ... /* 3 definitions in type refinement */ }]
- val decodes: IndexedSeq[Area { ... /* 7 definitions in type refinement */ }]
- val dispatches: Seq[Area { ... /* 4 definitions in type refinement */ }]
- val dpp: DecodePipelinePlugin
-
def
equals(obj: Any): Boolean
- Definition Classes
- OverridedEqualsHashCode → AnyRef → Any
- val executes: Seq[Area { ... /* 4 definitions in type refinement */ }]
- val fetch: Area { ... /* 4 definitions in type refinement */ }
-
def
foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit
- Definition Classes
- Nameable
- val fpp: FetchPipelinePlugin
-
def
getDisplayName(): String
- Definition Classes
- Nameable
-
def
getInstanceCounter: Int
- Definition Classes
- ContextUser
-
def
getName(default: String): String
- Definition Classes
- NameableByComponent → Nameable
-
def
getName(): String
- Definition Classes
- NameableByComponent → Nameable
-
def
getPartialName(): String
- Definition Classes
- Nameable
-
def
getPath(from: Component, to: Component): Seq[Component]
- Definition Classes
- NameableByComponent
-
def
getRefOwnersChain(): List[Any]
- Definition Classes
- OwnableRef
-
def
getScalaLocationLong: String
- Definition Classes
- ScalaLocated
-
def
getScalaLocationShort: String
- Definition Classes
- ScalaLocated
-
def
getScalaTrace(): Throwable
- Definition Classes
- ScalaLocated
-
val
globalData: GlobalData
- Definition Classes
- GlobalDataUser
-
def
hashCode(): Int
- Definition Classes
- OverridedEqualsHashCode → AnyRef → Any
-
def
isCompletelyUnnamed: Boolean
- Definition Classes
- Nameable
-
final
def
isNamed: Boolean
- Definition Classes
- Nameable
-
def
isPriorityApplicable(namePriority: Byte): Boolean
- Definition Classes
- Nameable
-
def
isUnnamed: Boolean
- Definition Classes
- NameableByComponent → Nameable
- val loadExecute: Area { ... /* 8 definitions in type refinement */ }
-
val
name: String
- Definition Classes
- Nameable
-
def
overrideLocalName(name: String): Logic.this.type
- Definition Classes
- Nameable
-
val
parentScope: ScopeStatement
- Definition Classes
- ContextUser
- val pbp: PipelineBuilderPlugin
- val perf: Area { ... /* 9 definitions in type refinement */ }
- val prediction: Area { ... /* 2 definitions in type refinement */ }
-
val
refOwner: RefOwnerType
- Definition Classes
- OwnableRef
- Annotations
- @DontName()
-
def
reflectNames(): Unit
- Definition Classes
- Nameable
- val reschedules: Area { ... /* 2 definitions in type refinement */ }
-
def
rework[T](body: ⇒ T): T
- Definition Classes
- Area
- val rfWrites: Area { val ports: Seq[spinal.lib.Flow[vexiiriscv.regfile.RegFileWriter]] }
-
val
scalaTrace: Throwable
- Definition Classes
- ScalaLocated
- def self: Logic
- val serializeds: IndexedSeq[Area { ... /* 7 definitions in type refinement */ }]
-
def
setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): Logic.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): Logic.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, postfix: String): Logic.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, namePriority: Byte): Logic.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable, weak: Boolean): Logic.this.type
- Definition Classes
- Nameable
-
def
setCompositeName(nameable: Nameable): Logic.this.type
- Definition Classes
- Nameable
-
def
setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): Logic.this.type
- Definition Classes
- Nameable
-
def
setName(name: String, namePriority: Byte): Logic.this.type
- Definition Classes
- Nameable
-
def
setName(name: String, weak: Boolean): Logic.this.type
- Definition Classes
- Nameable
-
def
setName(name: String): Logic.this.type
- Definition Classes
- Nameable
-
def
setNameAsWeak(): Logic.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String, namePriority: Byte, owner: Any): Logic.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String, namePriority: Byte): Logic.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String, weak: Boolean): Logic.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String, namePriority: Byte): Logic.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String, weak: Boolean): Logic.this.type
- Definition Classes
- Nameable
-
def
setPartialName(name: String): Logic.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable, name: String): Logic.this.type
- Definition Classes
- Nameable
-
def
setPartialName(owner: Nameable): Logic.this.type
- Definition Classes
- Nameable
-
def
setRefOwner(that: Any): Unit
- Definition Classes
- OwnableRef
-
def
setScalaLocated(source: ScalaLocated): Logic.this.type
- Definition Classes
- ScalaLocated
-
def
setWeakName(name: String): Logic.this.type
- Definition Classes
- Nameable
- val storeBroadcast: Area { ... /* 5 definitions in type refinement */ }
- val storeCommit: Area { ... /* 10 definitions in type refinement */ }
- val storeConditional: Area { ... /* 6 definitions in type refinement */ }
-
def
toString(): String
- Definition Classes
- Area → Nameable → AnyRef → Any
- val trap: Area { val ports: scala.collection.immutable.IndexedSeq[spinal.core.Area{val priv: spinal.core.Area{val pending: spinal.core.Area{val requests: scala.collection.mutable.ArrayBuffer[vexiiriscv.misc.AgedArbiterUp[vexiiriscv.misc.Trap]]; val arbiter: vexiiriscv.misc.AgedArbiter[vexiiriscv.misc.Trap]; val state: vexiiriscv.misc.Trap; val pc: spinal.core.UInt; val history: spinal.core.Bits; val slices: spinal.core.UInt; val xret: spinal.core.Area{val sourcePrivilege: spinal.core.UInt; val targetPrivilege: spinal.core.UInt}}; val exception: spinal.core.Area{val exceptionTargetPrivilegeUncapped: spinal.core.UInt; val code: spinal.core.Bits; val targetPrivilege: spinal.core.UInt}; val trigger: spinal.core.Area{val lanes: Seq[vexiiriscv.execute.ExecuteLanePlugin]; val oh: spinal.core.Bits; val valid: spinal.core.Bool; val reader: spinal.lib.TraversableOnceAnyPimped[spinal.lib.misc.pipeline.CtrlLaneApi#NodeMirror]#ReaderOh}; val whitebox: spinal.core.Area{val trap: spinal.core.Bool; val interrupt: spinal.core.Bool; val code: spinal.core.Bits}; val historyPort: spinal.lib.Flow[vexiiriscv.prediction.HistoryJump]; val pcPort: spinal.lib.Flow[vexiiriscv.fetch.JumpCmd]; val fsm: spinal.lib.fsm.StateMachine{val RESET: spinal.lib.fsm.State; val RUNNING: spinal.lib.fsm.State; val PROCESS: spinal.lib.fsm.State; val TRAP_EPC: spinal.lib.fsm.State; val TRAP_TVAL: spinal.lib.fsm.State; val TRAP_TVEC: spinal.lib.fsm.State; val TRAP_APPLY: spinal.lib.fsm.State; val XRET_EPC: spinal.lib.fsm.State; val XRET_APPLY: spinal.lib.fsm.State; val ATS_RSP: spinal.lib.fsm.State; val JUMP: spinal.lib.fsm.State; val LSU_FLUSH: spinal.lib.fsm.State; val FETCH_FLUSH: spinal.lib.fsm.State; val ENTER_DEBUG: spinal.lib.fsm.State; val DPC_READ: spinal.lib.fsm.State; val RESUME: spinal.lib.fsm.State; val inflightTrap: spinal.core.Bool; val holdPort: spinal.core.Bool; val wfi: spinal.core.Bool; val buffer: spinal.core.Area{val sampleIt: spinal.core.Bool; def sample[T <: spinal.core.Data](that: T): T; val i: spinal.core.Area{val valid: spinal.core.Bool; val code: spinal.core.Bits; val targetPrivilege: spinal.core.UInt}; val trap: spinal.core.Area{val interrupt: spinal.core.Bool; val targetPrivilege: spinal.core.UInt; val tval: spinal.core.Bits; val code: spinal.core.Bits}}; val resetToRunConditions: scala.collection.mutable.ArrayBuffer[spinal.core.Bool]; val atsPorts: spinal.core.Area{val refill: vexiiriscv.memory.AddressTranslationRefill; val invalidate: vexiiriscv.memory.AddressTranslationInvalidation; val invalidated: spinal.core.Bool}; val jumpTarget: spinal.core.UInt; val jumpOffset: spinal.core.UInt; val trapEnterDebug: spinal.core.Bool; val triggerEbreak: spinal.core.Bool; val triggerEbreakReg: spinal.core.Bool; val readed: spinal.core.Bits; val xretPrivilege: spinal.core.UInt}}; val valid: spinal.core.Bool; val interrupt: spinal.core.Bool; val cause: spinal.core.Bits}] }
-
def
unsetName(): Logic.this.type
- Definition Classes
- Nameable
-
def
valCallback[T](ref: T, name: String): T
- Definition Classes
- ValCallbackRec → ValCallback
-
def
valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit
- Definition Classes
- ValCallbackRec
-
def
valCallbackRec(obj: Any, name: String): Unit
- Definition Classes
- Area → ValCallbackRec
- val wfi: Bits
- val withCsr: Boolean
- def wrap[T <: Data](that: T): T