Packages

c

spinal.core.internals

PhaseVerilog

class PhaseVerilog extends PhaseMisc with VerilogBase

Linear Supertypes
VerilogBase, VhdlVerilogBase, PhaseMisc, Phase, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. PhaseVerilog
  2. VerilogBase
  3. VhdlVerilogBase
  4. PhaseMisc
  5. Phase
  6. AnyRef
  7. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new PhaseVerilog(pc: PhaseContext, report: SpinalReport[_])

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. val allocateAlgoIncrementaleBase: Int
  5. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  6. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @IntrinsicCandidate()
  7. def compile(component: Component): () ⇒ String
  8. def emitClockEdge(clock: String, edgeKind: EdgeKind): String
    Definition Classes
    VerilogBase
  9. def emitCommentAttributes(attributes: Iterable[Attribute]): String
    Definition Classes
    VerilogBase
  10. def emitCommentEarlyAttributes(attributes: Iterable[Attribute]): String
    Definition Classes
    VerilogBase
  11. def emitDirection(baseType: BaseType): String
    Definition Classes
    VerilogBase
  12. def emitEnumLiteral[T <: SpinalEnum](senum: SpinalEnumElement[T], encoding: SpinalEnumEncoding, prefix: String = "`"): String
    Definition Classes
    VerilogBase
  13. def emitEnumPackage(out: FileWriter): Unit
  14. def emitEnumType(senum: SpinalEnum, encoding: SpinalEnumEncoding, prefix: String = "`"): String
    Definition Classes
    VerilogBase
  15. def emitEnumType[T <: SpinalEnum](senum: SpinalEnumCraft[T], prefix: String): String
    Definition Classes
    VerilogBase
  16. def emitExpressionWrap(e: Expression, name: String, nature: String): String
    Definition Classes
    VerilogBase
  17. def emitExpressionWrap(e: Expression, name: String): String
    Definition Classes
    VerilogBase
  18. def emitFunctions(component: Component, ret: StringBuilder): Unit
  19. def emitQuotedString(string: String): String
    Definition Classes
    VerilogBase
  20. def emitRange(node: WidthProvider): String
    Definition Classes
    VerilogBase
  21. def emitResetEdge(reset: String, polarity: Polarity): String
    Definition Classes
    VerilogBase
  22. def emitStructType(struct: SpinalStruct): String
    Definition Classes
    VerilogBase
  23. def emitSyntaxAttributes(attributes: Iterable[Attribute]): String
    Definition Classes
    VerilogBase
  24. def emitType(e: Expression): String
    Definition Classes
    VerilogBase
  25. val emitedComponent: Map[ComponentEmitterTrace, Component]
  26. val emitedComponentRef: ConcurrentHashMap[Component, Component]
  27. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  28. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  29. def expressionAlign(net: String, section: String, name: String): String
    Definition Classes
    VerilogBase
  30. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  31. def getReEncodingFuntion(spinalEnum: SpinalEnum, source: SpinalEnumEncoding, target: SpinalEnumEncoding): String
    Definition Classes
    VerilogBase
  32. val globalPrefix: String
    Definition Classes
    VerilogBase
  33. def hasNetlistImpact: Boolean
    Definition Classes
    PhaseMisc → Phase
  34. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  35. def impl(pc: PhaseContext): Unit
    Definition Classes
    PhaseVerilog → Phase
  36. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  37. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  38. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  39. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  40. var outFile: FileWriter
  41. val romCache: HashMap[String, String]
  42. def rtlName: String
  43. def signalNeedProcess(baseType: BaseType): Boolean
    Definition Classes
    VerilogBase
  44. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  45. def targetPath: String
  46. val theme: Tab2
    Definition Classes
    VerilogBase
  47. def toString(): String
    Definition Classes
    AnyRef → Any
  48. val usedDefinitionNames: HashSet[String]
  49. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  50. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  51. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from VerilogBase

Inherited from VhdlVerilogBase

Inherited from PhaseMisc

Inherited from Phase

Inherited from AnyRef

Inherited from Any

Ungrouped