Packages

c

spinal.core.internals

ComponentEmitterVerilog

class ComponentEmitterVerilog extends ComponentEmitter

Linear Supertypes
ComponentEmitter, AnyRef, Any
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Inherited
  1. ComponentEmitterVerilog
  2. ComponentEmitter
  3. AnyRef
  4. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new ComponentEmitterVerilog(c: Component, systemVerilog: Boolean, verilogBase: VerilogBase, algoIdIncrementalBase: Int, mergeAsyncProcess: Boolean, asyncResetCombSensitivity: Boolean, anonymSignalPrefix: String, nativeRom: Boolean, nativeRomFilePrefix: String, caseRom: Boolean, emitedComponentRef: ConcurrentHashMap[Component, Component], emitedRtlSourcesPath: LinkedHashSet[String], pc: PhaseContext, spinalConfig: SpinalConfig, romCache: HashMap[String, String])

Type Members

  1. class AsyncProcess extends AnyRef
    Definition Classes
    ComponentEmitter
  2. class SyncGroup extends AnyRef
    Definition Classes
    ComponentEmitter

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. val _referenceSet: LinkedHashSet[String]
  5. var _referenceSetEnabled: Boolean
  6. def accessBitVectorFixed(e: BitVectorRangedAccessFixed): String
  7. def accessBitVectorFloating(e: BitVectorRangedAccessFloating): String
  8. def accessBoolFixed(e: BitVectorBitAccessFixed): String
  9. def accessBoolFloating(e: BitVectorBitAccessFloating): String
  10. val algoIdIncrementalBase: Int
    Definition Classes
    ComponentEmitterVerilog → ComponentEmitter
  11. var algoIdIncrementalOffset: Int
    Definition Classes
    ComponentEmitter
  12. def allocateAlgoIncremental(): Int
    Definition Classes
    ComponentEmitter
  13. def allocateAlgoIncrementale(): Int
    Definition Classes
    ComponentEmitter
  14. val analogs: ArrayBuffer[BaseType]
    Definition Classes
    ComponentEmitter
  15. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  16. val beginModule: StringBuilder
  17. def boolLiteralImpl(e: BoolLiteral): String
  18. val c: Component
  19. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @IntrinsicCandidate()
  20. def commentTagsToString(host: SpinalTagReady, comment: String): String
    Definition Classes
    ComponentEmitter
  21. def component: Component
    Definition Classes
    ComponentEmitterVerilog → ComponentEmitter
  22. val createInterfaceWrap: LinkedHashMap[Data, String]
    Definition Classes
    ComponentEmitter
  23. def cutLongExpressions(): Unit
    Definition Classes
    ComponentEmitter
  24. val declarations: StringBuilder
  25. val declaredInterface: HashSet[Interface]
  26. val definitionAttributes: StringBuilder
  27. def dispatchExpression(e: Expression): String
  28. def elaborate(): Unit
    Definition Classes
    ComponentEmitter
  29. def emitAnalogs(): Unit
  30. def emitArchitecture(): Unit
  31. def emitAssignedExpression(that: Expression): String
  32. def emitAsynchronous(process: AsyncProcess): Unit
  33. def emitAsynchronousAsAsign(process: AsyncProcess): Boolean
  34. def emitBaseTypeSignal(baseType: BaseType, name: String): String
  35. def emitBaseTypeWrap(baseType: BaseType, name: String): String
  36. def emitBeginEndModule(): Unit
  37. def emitBitVectorLiteral(e: BitVectorLiteral): String
  38. def emitClockedProcess(emitRegsLogic: (String, StringBuilder) ⇒ Unit, emitRegsInitialValue: (String, StringBuilder) ⇒ Unit, b: StringBuilder, clockDomain: ClockDomain, withReset: Boolean): Unit
  39. def emitEntity(): Unit
  40. def emitEnumDebugLogic(): Unit
  41. def emitEnumLiteralWrap(e: EnumLiteral[_ <: SpinalEnum]): String
  42. def emitEnumParams(): Unit
  43. def emitEnumPoison(e: EnumPoison): String
  44. def emitExpression(that: Expression): String
  45. def emitExpressionNoWrappeForFirstOne(that: Expression): String
  46. def emitInitials(): Unit
  47. def emitInterfaceSignal(data: Interface, name: String): String
  48. def emitLeafStatements(statements: ArrayBuffer[LeafStatement], statementIndexInit: Int, scope: ScopeStatement, assignmentKind: String, b: StringBuilder, tab: String): Int
  49. def emitLocation(that: AssignmentStatement): String
  50. def emitMaskedLiteral(e: MaskedLiteral): String
  51. def emitMem(mem: Mem[_]): Unit
  52. def emitMems(mems: ArrayBuffer[Mem[_]]): Unit
  53. def emitMuxes(): Unit
  54. def emitReference(that: DeclarationStatement, sensitive: Boolean): String
  55. def emitReferenceNoOverrides(that: DeclarationStatement): String
  56. def emitSignals(): Unit
  57. def emitSubComponents(openSubIo: HashSet[BaseType]): Unit
  58. def emitSynchronous(component: Component, group: SyncGroup): Unit
  59. val endModule: StringBuilder
  60. val enumDebugStringList: ArrayBuffer[(SpinalEnumCraft[_ <: SpinalEnum], String, Int)]
  61. def enumEgualsImpl(eguals: Boolean, sim: Boolean)(e: BinaryOperator with EnumEncoded): String
  62. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  63. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  64. val expressionToWrap: LinkedHashSet[Expression]
    Definition Classes
    ComponentEmitter
  65. def fillExpressionToWrap(): Unit
  66. def getBaseTypeSignalInitBoot(signal: BaseType): String
  67. def getBaseTypeSignalRandBoot(signal: BaseType): String
  68. def getBaseTypeSignalSimInit(signal: BaseType): String
  69. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  70. def getOrDefault[X, Y](map: ConcurrentHashMap[X, Y], key: X, default: Y): Y
    Definition Classes
    ComponentEmitter
  71. def getTrace(): ComponentEmitterTrace
  72. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  73. def idToBits[T <: SpinalEnum](senum: SpinalEnumElement[T], encoding: SpinalEnumEncoding): String
  74. val initials: ArrayBuffer[LeafStatement]
    Definition Classes
    ComponentEmitter
  75. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  76. def isSubComponentInputBinded(data: BaseType): Expression
    Definition Classes
    ComponentEmitter
  77. def isSubComponentInputBound(data: BaseType): Expression
    Definition Classes
    ComponentEmitter
  78. val localEnums: LinkedHashSet[(SpinalEnum, SpinalEnumEncoding)]
  79. val localparams: StringBuilder
  80. val logics: StringBuilder
  81. var memBitsMaskKind: MemBitsMaskKind
  82. val mems: ArrayBuffer[Mem[_]]
    Definition Classes
    ComponentEmitter
  83. val mergeAsyncProcess: Boolean
    Definition Classes
    ComponentEmitterVerilog → ComponentEmitter
  84. val multiplexersPerSelect: LinkedHashMap[(Expression with WidthProvider, Int), ArrayBuffer[Multiplexer]]
    Definition Classes
    ComponentEmitter
  85. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  86. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  87. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  88. val openSubIo: HashSet[BaseType]
    Definition Classes
    ComponentEmitter
  89. def operatorImplAsBinaryOperator(verilog: String)(e: BinaryOperator): String
  90. def operatorImplAsBinaryOperatorLeftSigned(vhd: String)(op: BinaryOperator): String
  91. def operatorImplAsBinaryOperatorSigned(vhd: String)(op: BinaryOperator): String
  92. def operatorImplAsCat(e: Operator.Bits.Cat): String
  93. def operatorImplAsEnumToEnum(e: CastEnumToEnum): String
  94. def operatorImplAsMux(e: BinaryMultiplexer): String
  95. def operatorImplAsNoTransformation(func: Cast): String
  96. def operatorImplAsUnaryOperator(verilog: String)(e: UnaryOperator): String
  97. def operatorImplResize(func: Resize): String
  98. def operatorImplResizeSigned(func: Resize): String
  99. def outSigCanInline(sig: BaseType): Boolean
  100. val outputNoNeedWrap: LinkedHashSet[Expression]
  101. val outputSignalNoUse: LinkedHashSet[BaseType]
  102. val outputWrap: LinkedHashMap[Expression, String]
  103. val outputsToBufferize: LinkedHashSet[BaseType]
    Definition Classes
    ComponentEmitter
  104. val portMaps: ArrayBuffer[String]
  105. val processes: LinkedHashSet[AsyncProcess]
    Definition Classes
    ComponentEmitter
  106. val randBoots: ArrayBuffer[BaseType]
  107. def readedOutputWrapEnable: Boolean
    Definition Classes
    ComponentEmitter
  108. def refImpl(e: BaseType): String
  109. def referenceSetAdd(str: String): Unit
  110. def referenceSetPause(): Unit
  111. def referenceSetResume(): Unit
  112. def referenceSetSorted(): LinkedHashSet[String]
  113. def referenceSetStart(): Unit
  114. def referenceSetStop(): Unit
  115. val referencesOverrides: HashMap[Nameable, Any]
    Definition Classes
    ComponentEmitter
  116. def result: String
  117. def shiftLeftByIntFixedWidthImpl(e: ShiftLeftByIntFixedWidth): String
  118. def shiftLeftByIntImpl(e: ShiftLeftByInt): String
  119. def shiftLeftByUIntImpl(e: ShiftLeftByUInt): String
  120. def shiftLeftByUIntImplSigned(e: ShiftLeftByUInt): String
  121. def shiftRightByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String
  122. def shiftRightByIntImpl(e: ShiftRightByInt): String
  123. def shiftRightSignedByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String
  124. def signalNoUse(sig: BaseType): Boolean
  125. val spinalConfig: SpinalConfig
    Definition Classes
    ComponentEmitterVerilog → ComponentEmitter
  126. val subComponentInputToNotBufferize: HashSet[Any]
    Definition Classes
    ComponentEmitter
  127. val syncGroups: LinkedHashMap[(ClockDomain, ScopeStatement, Boolean, Any), SyncGroup]
    Definition Classes
    ComponentEmitter
  128. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  129. def toString(): String
    Definition Classes
    AnyRef → Any
  130. var verilogIndexGenerated: Boolean
  131. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  132. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  133. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  134. def wrapSubInput(io: BaseType): Unit
    Definition Classes
    ComponentEmitterVerilog → ComponentEmitter
  135. val wrappedExpressionToName: HashMap[Expression, String]
    Definition Classes
    ComponentEmitter

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from ComponentEmitter

Inherited from AnyRef

Inherited from Any

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