Type Members

1.  case class Swd(useSwclk: Boolean = true) extends Bundle with IMasterSlave with Product with Serializable

   ARM Serial Wire Debug (ADIv5/ADIv6) pins: a probe-driven clock and one bidirectional data line.

   ARM Serial Wire Debug (ADIv5/ADIv6) pins: a probe-driven clock and one bidirectional data line.

   SWDIO is push-pull tristate, not open-drain: the host drives 0 and 1 during the request, WDATA and line reset, the target drives 0 and 1 during ACK and RDATA, and both release the line for the turnarounds. Hence a TriState, which InOutWrapper turns into a real inout.

   master = the host (debug probe), slave = the target. Both ends own a tristate driver, so asSlave() is not the plain flip of asMaster(): only SWCLK changes direction.

2.  case class SwdApCmd() extends Bundle with Product with Serializable

   ADI SW-DP: DPIDR, CTRL/STAT, SELECT, RDBUFF/RESEND, ABORT, sticky-error and WAIT/FAULT gating, posted AP reads.

   ADI SW-DP: DPIDR, CTRL/STAT, SELECT, RDBUFF/RESEND, ABORT, sticky-error and WAIT/FAULT gating, posted AP reads. Access ports hang off ap.cmd / ap.rsp — one outstanding AP transaction at a time, completed by a single ap.rsp pulse. Runs in the SWCLK domain.

   dpidr defaults to a placeholder: pick your own designer/part encoding, and do not reuse an ARM Cortex SW-DP value (debuggers key target detection off it).

3.  case class SwdApRsp() extends Bundle with Product with Serializable
4.  case class SwdDp(dpidr: BigInt = BigInt("0BA11AAB", 16)) extends Component with Product with Serializable
5.  case class SwdDpCmd() extends Bundle with Product with Serializable

   SWD wire protocol (ADIv6 B4): bit-level framing of one packet — request, turnaround, ACK, data phase, line reset.

   SWD wire protocol (ADIv6 B4): bit-level framing of one packet — request, turnaround, ACK, data phase, line reset. Runs in the SWCLK domain (see Swd.clockDomain) and knows nothing about DP/AP registers: it hands each request to a DP over dp.cmd / dp.rsp / dp.wr.

   The DP must answer dp.cmd combinationally (rsp.valid in the same cycle): that cycle is the turnaround, and ACK[0] goes on the wire on the next SWCLK. The PHY cannot stall the host.

6.  case class SwdDpRsp() extends Bundle with Product with Serializable
7.  case class SwdDpWrite() extends Bundle with Product with Serializable
8.  case class SwdPhy() extends Component with Product with Serializable
9.  case class SwdPhyDp(dpidr: BigInt = BigInt("0BA11AAB", 16)) extends Component with Product with Serializable