The commit logic is mostly composed :

  • Reschedule status Which specifies the older ROB ID on which a jump / trap is pending.

  • Commit Logic Which waits for the older instruction completion before committing it, and eventually applying some reschedule.


Register file

Currently, the register file is inferred into simple dual-port distributed ram :

  • Each write port will create its own bank

  • Each read port will read each bank, and mux the correct one using a distributed-ram-xor-based LVT (live value table)