What is the overhead of SpinalHDL generated RTL compared to human written VHDL/Verilog?
The overhead is null, SpinalHDL is not an HLS approach. Its goal is not to translate any arbitrary code into RTL, but to provide a powerful language to describe RTL and rise the abstraction level.
What if SpinalHDL becomes unsupported in the future?
Does SpinalHDL keep comments in generated VHDL/verilog?
No, it doesn’t. Generated files should be considerate as a netlist. For example, when you compile C code, do you care about your comments in the generated assembly code?
Could SpinalHDL scale up to big projects?
Yes, some experiments were done, and it appears that generating hundreds of 3KLUT CPUs with caches takes something like 12 seconds, which is a ridiculous time compared to the time required to simulate or synthesize this kind of design.
How SpinalHDL came to be
Between December 2014 and April 2016, it was as a personal hobby project. But since April 2016 one person is working full time on it. Some people are also regularly contributing to the project.
Why develop a new language when there is VHDL/Verilog/SystemVerilog
This page is dedicated to this topic.
How to use an unreleased version of SpinalHDL (but commited on git)
For instance, if you wanna try the
dev branch, do the following in a dummy folder :
git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev
sbt clean publishLocal