SpinalHDL
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Core
Lib
Symbolic
Data types
Bool
Bits
UInt/SInt
SpinalEnum
Bundle
Vec
UFix/SFix
Floating
Structuring
Component and hierarchy
Area
Function
Clock domains
Instantiate VHDL and Verilog IP
Semantic
Assignments
When/Switch/Mux
Rules
Sequential logic
Registers
RAM/ROM
Design errors
Assignement overlap
Clock crossing violation
Combinational loop
Hierarchy violation
Io bundle
Latch detected
No driver on
NullPointerException
Register defined as component input
Scope violation
Spinal can’t clone class
Unassigned register
Unreachable is statement
Width mismatch
Other language features
Utils
Assertions
Formal
Analog and inout
VHDL and Verilog generation
Libraries
Utils
Stream
Flow
Fragment
State machine
VexRiscv (RV32IM CPU)
Bus Slave Factory
Bus
AHB-Lite3
Apb3
Axi4
AvalonMM
Com
UART
IO
ReadableOpenDrain
TriState
Graphics
Colors
VGA
EDA
QSysify
Simulation
Setup and installation
Boot a simulation
Accessing signals of the simulation
Clock domains
Thread-full API
Thread-less API
Simulation engine
Examples
Asynchronous adder
Dual clock fifo
Single clock fifo
Synchronous adder
Uart decoder
Uart encoder
Examples
Simple ones
APB3 definition
Carry adder
Color summing
Counter with clear
Introduction
PLL BlackBox and reset controller
RGB to gray
Sinus rom
Intermediates ones
Fractal calculator
UART
VGA
Advanced ones
JTAG TAP
Memory mapped UART
Pinesec
Timer
Legacy
RiscV
pinsec
Hardware
SoC toplevel (Pinsec)
Introduction
Software
Developers area
Bus Slave Factory Implementation
How to HACK this documentation
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Users
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Compagnies
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QsPin, Belgium
Repositories
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J1Sc Stack CPU
VexRiscv CPU and SoC
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v: v1.3.8
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