case class Axi4Master(axi: Axi4, clockDomain: ClockDomain, name: String = "unnamed") extends Product with Serializable
Simulation master for the Axi4 bus protocol spinal.lib.bus.amba4.axi.Axi4.
- axi
bus master to drive
- clockDomain
clock domain to sample data on
SimConfig.compile(new Component { val io = new Bundle { val axiSlave = slave(Axi4(Axi4Config(32, 32))) } io.axiSlave.assignDontCare }).doSim("sample") { dut => val master = Axi4Master(dut.io.axiSlave, dut.clockDomain) val data = master.read(0x1000, 4) }
- Alphabetic
- By Inheritance
- Axi4Master
- Serializable
- Serializable
- Product
- Equals
- AnyRef
- Any
- Hide All
- Show All
- Public
- All
Instance Constructors
-
new
Axi4Master(axi: Axi4, clockDomain: ClockDomain, name: String = "unnamed")
create a new simulation master with the given bus instance and clock domain.
create a new simulation master with the given bus instance and clock domain.
- axi
bus master to drive
- clockDomain
clock domain to sample data on
Value Members
-
final
def
!=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
final
def
##(): Int
- Definition Classes
- AnyRef → Any
-
final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
- val axi: Axi4
- val clockDomain: ClockDomain
-
def
clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native() @IntrinsicCandidate()
-
final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
-
def
idle: Boolean
check if bus master is idle (readIdle && writeIdle)
-
final
def
isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val name: String
-
final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
final
def
notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
-
final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
-
def
read(address: BigInt, totalBytes: BigInt, id: Int = 0, burst: Axi4Burst = Incr, len: Int = 0, size: Int = maxSize): List[Byte]
Read synchronously multiple bytes from the specified address.
Read synchronously multiple bytes from the specified address.
- address
address to read from; does not need to be aligned (data will be truncated automatically)
- totalBytes
total number of bytes in the result; if longer than a single transaction (as specified by
burst
,len
, andsize
), the bus master will issue multiple transactions- id
AxID to use in the request; xID in the response will be checked against this (cf. AXI specification)
- burst
burst mode to issue (cf. AXI specification)
- len
number of beats in a single transaction minus one (cf. AXI specification)
- size
number of bytes in one beat, log encoded (cf. AXI specification)
-
def
readCB(address: BigInt, totalBytes: BigInt, id: Int = 0, burst: Axi4Burst = Incr, len: Int = 0, size: Int = maxSize)(callback: (List[Byte]) ⇒ Unit): Unit
Read asynchronously; same as
read
, but result is delivered in a callbackRead asynchronously; same as
read
, but result is delivered in a callback- callback
callback function on finish
-
def
readIdle: Boolean
check if all read channels are idle (no read transactions active)
-
def
readSingle(address: BigInt, totalBytes: Int, id: Int = 0, burst: Axi4Burst = Incr, len: Int = 0, size: Int = maxSize)(callback: (List[Byte]) ⇒ Unit): Unit
Read asynchronously with only one transaction
-
def
reset(): Unit
Reset bus master (dropping all pending transactions)
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
-
final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
final
def
wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native()
-
final
def
wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
def
write(address: BigInt, data: List[Byte], id: Int = 0, burst: Axi4Burst = Incr, len: Int = 0, size: Int = maxSize): Unit
Write synchronously multiple bytes to the specified address.
Write synchronously multiple bytes to the specified address.
- address
address to write to; does not need to be aligned (data will be truncated automatically)
- data
list of bytes to write to address; if longer than a single transaction (as specified by
burst
,len
, andsize
), the bus master will issue multiple transactions- id
AxID to use in the request; xID in the response will be checked against this (cf. AXI specification)
- burst
burst mode to issue (cf. AXI specification)
- len
number of beats in a single transaction minus one (cf. AXI specification)
- size
number of bytes in one beat, log encoded (cf. AXI specification)
-
def
writeCB(address: BigInt, data: List[Byte], id: Int = 0, burst: Axi4Burst = Incr, len: Int = 0, size: Int = maxSize)(callback: ⇒ Unit): Unit
Write asynchronously; same as
write
, but completion is delivered in a callbackWrite asynchronously; same as
write
, but completion is delivered in a callback- callback
callback function on finish
-
def
writeIdle: Boolean
check if all write channels are idle (no write transactions active)
-
def
writeSingle(address: BigInt, data: List[Byte], id: Int = 0, burst: Axi4Burst = Incr, len: Int = 0, size: Int = maxSize)(callback: ⇒ Unit): Unit
Write asynchronously with only one transaction
Deprecated Value Members
-
def
finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( classOf[java.lang.Throwable] ) @Deprecated
- Deprecated