Packages

c

spinal.lib.bus.amba4.axi.sim

AxiMemorySim

case class AxiMemorySim(axi: Axi4, clockDomain: ClockDomain, config: AxiMemorySimConfig) extends Product with Serializable

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Serializable, Serializable, Product, Equals, AnyRef, Any
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  1. AxiMemorySim
  2. Serializable
  3. Serializable
  4. Product
  5. Equals
  6. AnyRef
  7. Any
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Visibility
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Instance Constructors

  1. new AxiMemorySim(axi: Axi4, clockDomain: ClockDomain, config: AxiMemorySimConfig)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  5. val axi: Axi4
  6. val busWordWidth: Int

    Bus word width in bytes

  7. val clockDomain: ClockDomain
  8. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @IntrinsicCandidate()
  9. val config: AxiMemorySimConfig
  10. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  11. def getBurst(ax: Axi4Ax): Int
  12. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  13. def getId(ax: Axi4Ax): Long
  14. def getLen(ax: Axi4Ax): Int
  15. def getSize(ax: Axi4Ax): Int
  16. def getSizeAndCheck(ax: Axi4Ax): Int
  17. def getStrb(w: Axi4W): BigInt
  18. def handleAr(ar: Stream[Axi4Ar]): Unit
  19. def handleAw(aw: Stream[Axi4Aw]): Unit
  20. def handleAwAndW(w: Stream[Axi4W], aw: Stream[Axi4Aw], b: Stream[Axi4B]): Unit

    Handle write command, write, and write response channel as implemented by Altera/Intel on their Cyclone 5 platform.

    Handle write command, write, and write response channel as implemented by Altera/Intel on their Cyclone 5 platform. Their implementation behaves as all three channels are coupled. The implementation waits until all words for a write operation have been transfered. Then it asserts the AWREADY to accept the write command. After that, BVALID is asserted.

    w

    AXI write channel

    aw

    AXI write command channel

    b

    AXI write response channel

  21. def handleR(r: Stream[Axi4R]): Unit
  22. def handleW(w: Stream[Axi4W], b: Stream[Axi4B]): Unit
  23. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  24. val maxBurstSize: Int
  25. val memory: SparseMemory
  26. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  27. def newAxiJob(ax: Axi4Ax): AxiJob
  28. def newAxiJob(address: Long, burstLength: Int, burstSize: Int, burstType: Int, id: Long): AxiJob
  29. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  30. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  31. val pending_reads: Queue[AxiJob]
  32. val pending_writes: Queue[AxiJob]
  33. def reset(): Unit
  34. def setLast(r: Axi4R, last: Boolean): Unit
  35. def start(): Unit
  36. def stop(): Unit
  37. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  38. val threads: Queue[SimThread]
  39. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  40. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  41. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from Serializable

Inherited from Serializable

Inherited from Product

Inherited from Equals

Inherited from AnyRef

Inherited from Any

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